在商業上已經有人使用先進的2.5D FPGA，它比起傳統FPGA具有更大的邏輯閘容量，以及更多的腳位數量。有些多重FPGA系統會使用此先進的2.5D FPGA。
商業使用的2.5D FPGA是由數個晶粒透過載板連接而組成的。
載板提供一部分晶粒之間互相連接的資源，晶粒之間互相連接的資源與晶粒之中的連接相比會造成額外的信號延遲。
最近的ㄧ份研究顯示，當一個電路被映射到一個2.5D FPGA過程中減少信號在晶粒之間的傳遞，可以在多重2.5D FPGA系統的可佈線性和時序上獲得更好的表現。
在一個多重2.5D FPGA系統中，FPGA之間的連接是由多條硬體接線連接，在這系統中可能會有成千上萬FPGA之間的內部信號與一個FPGA相關，而在這時腳位定位會對晶粒之間的信號交叉量有極大的影響。
在這篇論文中，我們對這種系統創制了系統腳位定位問題，這個問題的目標是最小化單一FPGA中晶粒之間的信號交叉量。
我們在系統腳位定位問題中考慮2.5D FPGA的多重晶粒結構，進而提出一個有效且效率很高的迭代改進演算法，此演算法使用整數線性規劃去實現。
拿我們的實驗結果與其它兩個啟發式演算法相比，發現我們的演算法在單一個FPGA中晶粒之間的信號交叉量可以減少30\%以上。

Advanced 2.5D FPGAs with larger logic capacity and higher
pin counts compared to conventional FPGAs are commercially
available. Some multi-FPGA systems have already utilized
2.5D FPGAs.
Commercial 2.5D FPGA consists of multiple dies connected
through an interposer.
The interposer provides a fraction of the amount of
interconnect resources with increased delay compared
to that within individual dies.
A recent study has shown the benefits
of reducing signal crossings between dies on routability
and timing when a circuit is mapped to a 2.5D FPGA.
In a multi-2.5D FPGA system with multiplexed hardwired
inter-FPGA connections, there can be tens of thousands
of inter-FPGA signals incident with each FPGA and their
pin assignment can greatly affect
the amount of signal crossings between dies.
In this paper, we formulate the pin assignment problem
for such system with the objective of
minimizing signal crossings between dies within the individual
FPGAs.
Taking into consideration of the multi-die structure of
2.5D FPGA, we propose an effective and efficient
iterative improvement
algorithm based on integer linear programming to the
pin assignment problem.
Experimental results show that our algorithm can reduce signal
crossings between dies in the individual FPGAs by over
30\% on average compared to two heuristic approaches.

致謝 v
Acknowledgements vii
摘要 ix
Abstract xi
1 Introduction 1
1.1 Multi-FPGA Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 2.5D FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 SLR crossings in 2.5D FPGA . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Preliminaries 4
2.1 Targeted Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Compilation Flow of Multi-FPGA System . . . . . . . . . . . . . . . . 5
2.3 Previous Works on Pin Assignment . . . . . . . . . . . . . . . . . . . . 7
2.4 SLR-Aware Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Algorithm 10
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Considering Different Ordering of FPGAs . . . . . . . . . . . . . . . . 12
3.3 Initial Feasible Pin Assignment Generation . . . . . . . . . . . . . . . 12
3.4 Pin Assignment Refinement . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Considering Maximum Allowance Of SLR Crossings Between Dies . . 17
4 Experimental Results 19
5 Conclusion 27
References 28
A Illustrative Example 30

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