在現今的的積體電路設計之中，配置臨界電壓是一個能夠非常有效降低漏電功耗的技術。隨著先進製程演進，特徵尺寸持續縮小的情況下，在決定裝置之臨界電壓的佈植區域上的佈局限制(我們稱為MinIA限制)變得越來越難滿足。因此，我們需要在擺放時將這些限制同時考慮。我們解釋了\cite{intraminia}在給定原先元件擺放位置下同時考慮細部擺放及改善臨界電壓以解決佈局上所有違反MinIA限制的方法。這是第一篇提出最佳且有效率使用綜合整數線性規劃為基礎之演算法來處理同列中MinIA之限制的研究。我們並且延伸此之演算法同時處裡同一列中以及列與列之間的MinIA限制。我們所提出演算法可能夠保證完全解決所有違反MinIA限制之情況。實驗數據顯示此研究所提出之的演算法僅少量影響原有擺放位置及臨界電壓配置，並可於實務上快速消除所有違反MinIA情形。

Threshold voltage assignment is a very effective technique to reduce
leakage power consumption in modern integrated circuit (IC) design. As
feature size continues to decrease, the layout constraints (called MinIA constraints)
on the implant area, which determines the threshold voltage of a
device, are becoming increasingly difficult to satisfy. It is necessary to take
these constraints into consideration during the placement stage. [1] proposes
to resolve the MinIA constraint violations of a given placement by
performing simultaneous detailed placement and threshold voltage refinement.
They first present an optimal and efficient mixed integer-linear programming
(MILP)-based algorithm to handle intra-row MinIA constraints.
We then extend the MILP-based algorithm to handle both inter-row and intrarow
MinIA constraints. Our algorithm guarantees to fix all MinIA constraint
violations. Experimental results demonstrate that our algorithm only
perturb the original placement and threshold voltage assignment solutions
minimally to eliminate all violations and are fast in practice.

Contents
誌謝 v
Acknowledgements vii
摘要 ix
Abstract xi
1 Introduction 1
1.1 Detail Placement Refinement . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Multiple Threshold Voltages Assignment . . . . . . . . . . . . . . . . 2
1.3 Filler Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Handling MinIA Constraints . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Preliminary 7
2.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Useful Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Handling Intra-row MinIA Design Rules 11
3.1 ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 A Simpler and Faster MILP Model . . . . . . . . . . . . . . . . . . . . 15
3.3 Efficiency of the Model . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Dealing with Fixed Macros . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Handling Both Intra-row and Inter-row MinIA Design Rules 19
4.1 Inter-Row MinIA Design Rules . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Additional Constraints for Inter-Row MinIA Design Rules . . . . . . . 20
4.3 Speedup Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Experimental Results 25
6 Conclusions 31
References 33

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