近年來，臨界邏輯因為其實體實現的進展以及其和類神經網路的高度關連，吸引
許多研究的關注。另一方面，近似運算為針對可容忍錯誤之應用的新設計範例，
這類的應用如機器學習、形態辨識. . . . . .等。我們將於此論文提出結合臨界邏輯與近似運算的合成演算法，透過我們提出的演算法，我們可以在保證錯誤率的限
制下，得到具成本效益的近似臨界邏輯電路。我們在IWLS2005的電路上進行實
驗，實驗結果顯示我們提出的演算法能有效的探索給定之臨界邏輯電路的可近似
性。以5%的錯誤率為例，臨界邏輯電路成本平均可得到22.8%的改善。

Recently, threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks.On the other hand, approximate computing is a new design paradigm that focuses on error-tolerant applications, e.g., machine learning or pattern recognition.In this thesis, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee.We conduct experiments on a set of IWLS 2005 benchmarks.The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark.For a 5\% error rate constraint, the circuit cost can be reduced by 22.8\% on average.

1 Introduction 1
2 Preliminaries 3
2.1 LTG and threshold function . . 3
2.2 Positive-negative weight transformation . . 4
2.3 Critical-Eect Vector . . 4
2.4 Hybrid cost function of LTG networks . . 5
3 Proposed Method 7
3.1 Error rate computation . . 7
3.2 Approximate operations . . 8
3.3 LTG and approximate operation candidate selection . . 9
3.4 Error rate estimation after approximation . . 10
3.5 Approximation heuristic . . 14
3.6 Redundancy removal . . 16
3.7 Overall flow .. 17
4 Experimental results 19
5 Conclusion 22

[1] C. Augustine et al., Low-power functionality enhanced computation architecture using spin-based devices," Proc. Int. Symp. on Nanoscale Architecture, 2011, pp. 129-136.
[2] M. J. Avedillo et al., Multi-Threshold Threshold Logic Circuit Design using Resonant Tunnelling Devices," Electron. Lett., 2003, pp. 1502-1504, vol. 39.
[3] I.A. Basheer et al., Articial neural networks: fundamentals, computing, design, and application," Journal of Microbiological Methods, 2000, pp. 3-31.
[4] V. Beiu et al., VLSI Implementations of Threshold Logic-A Comprehensive Survey," IEEE Transactions on Neural Networks, 2003, pp. 1217-1243, vol. 14.
[5] V. Beiu, On Existential and Constructive Neural Complexity Results," Neural Networks and Computational Intelligence, 2003, pp. 63-72.
[6] Y.-C. Chen et al., Fast Synthesis of Threshold Logic Networks with Optimization," Proc. ASP-DAC, 2016, pp. 486-491.
[7] Y.-C. Chen et al., Automated Mapping for Recongurable Single-Electronn Transistor arrays," Proc. DAC, 2011, pp. 878-883.
[8] Y.-C. Chen et al., A Synthesis Algorithm for Recongurable Single-Electron Transistor Arrays," ACM Journal on Emerging Technologies in Computing System, 2013, Article 5, vol. 9.
[9] C.-E. Chiang et al., On Recongurable Single-Electron Transistor Arrays Synthesis using Reordering Techniques," Proc. DATE, 2013, pp. 1807-1812.
[10] V. Chippa et al., Analysis and characterization of inherent application resilience for approximate computing," Proc. DAC, 2013, pp. 1-9.
[11] V. Chippa et al., Dynamic effort scaling: Managing the quality-efficiency tradeoff." Proc. DAC, 2011. pp. 603-608.
[12] L. O. Chua et al., Cellular neural networks: applications" IEEE Transactions on Circuits and Systems, 1988, pp. 1273-1290.
[13] S. Eachempati et al., Recongurable Bdd-based Quantum Circuits," Proc. Int. Symp. on Nanoscale Architectures, 2008, pp. 61-67.
[14] D. Goldharber-Gordon et al., Overview of Nanoelectronic Devices," Proc. IEEE, 1997, pp. 521-540.
[15] T. Gowda et al., A Non-ILP Based Threshold Logic Synthesis Methodology," Proc. International Workshop on Logic and Synthesis, 2007, pp. 222-229.
[16] T. Gowda et al., Decomposition Based Approach for Synthesis of Multi-Level Threshold Logic Circuits," Proc. ASP-DAC, 2008, pp. 125-130.
[17] T. Gowda et al., Identfication of Threshold Functions and Synthesis of Threshold Networks," IEEE Transactions CAD, 2011, pp. 665-677, vol. 30.
[18] T. Gowda et al., Combinational Equivalence Checking for Threshold Logic Circuits," Proc. Great Lake Symp. VLSI, 2007, pp. 102-107.
[19] P. Gupta et al., Automatic Test Generation for Combinational Threshold Logic Networks," IEEE Transactions CAD, 2008, pp. 1035-1045, vol. 16.
[20] V. Gupta et al., IMPACT: imprecise adders for low-power approximate computing" Proc. ISLPED, 2011. pp. 409-414.
[21] V. Gupta et al., Low-power digital signal processing using approximate adders," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, pp. 124-137. vol. 32.
[22] J. Han et al., Approximate computing: An emerging paradigm for energy-efficient design," Proc. ETS, 2013, pp. 1-6.
[23] G. B. Huang et al., Can threshold networks be trained directly?," IEEE Transactions on Circuits and Systems II: Express Briefs, 53(3), 2006, pp. 187-191.
[24] M. Imani et al., Resistive configurable associative memory for approximate computing," Proc. DATE, 2016, pp. 1327-1332.
[25] Y. Jin et al., Pareto-Based Multiobjective Machine Learning: An Overview and Case Studies," IEEE Transactions on Systems, 2008, pp. 397-415.
[26] P.-Y. Kuo et al., On Rewiring and Simplfication for Canonicity in Threshold Logic Circuits," Proc. ICCAD, 2011, pp. 396-403.
[27] C. Lageweg et al., A Linear Threshold Gate Implementation in Single Electron Technology," Proc. Comput. Soc. Workshop VLSI, 2001, pp. 93-98.
[28] N.-Z. Lee et al., Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits," Proc. ICCAD, 2016, pp. 1-8.
[29] C.-C. Lin, et al., In&Out: Restructuring for Threshold Logic Network Optimization", Proc. ISQED, 2017, pp. 413-418.
[30] C.-C. Lin et al., Rewiring for Threshold Logic Circuit Minimization," Proc.DATE, 2014, pp. 1-6.
[31] R. Lippmann. An introduction to computing with neural nets," IEEE ASSP Magazine, 4(2), 1987, pp. 4-22.
[32] J. Miao et al., Multi-level approximate logic synthesis under general error constraints," Proc. ICCAD, 2014. pp. 504-510.
[33] S. Muroga, Threshold Logic and its Applications," 1971, New York, NY: John Wiley.
[34] S. H. Nawab et al., Approximate signal processing," VLSI Signal Processing, 1997.
[35] A. Neutzling et al., Threshold Logic Synthesis Based on Cut Pruning," Proc. ICCAD, 2015, pp. 494-499.
[36] C. Pacha et al., Resonant Tunneling Device Logic Circuit," 1999, DortmundGerhard-Mercator University of Duisburg, Germany, Tech. Rep.
[37] M. Perkowski et al., Logic Synthesis for Regular Fabric Realized in Quantum dot Cellular Automata," Journal of Multiple-Valued Logic and Soft Comput., 2004, pp. 768-773.
[38] V. Saripalli et al., Energy-delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits," Journal of Low Power Electronics, 2010, pp. 415-428,vol. 6.
[39] C.-K. Tsai et al., Sensitization Criterion for Threshold Logic Circuits and its Application," Proc. ICCAD, 2013, pp. 226-233.
[40] P. Venkataramani et al., Sequential Circuit Design in Quantumdot Cellular Automata," Proc. Nanotechnology Conf., 2008, pp. 534-537.
[41] S. Venkataramani et al., Quality programmable vector processors for approximate computing." Proc. 46th Annual IEEE/ACM Int. Symp. on Microarchitecture, 2013. pp. 1-12.
[42] S. Venkataramani et al., SALSA: Systematic logic synthesis of approximate circuits," Proc. DAC, 2012, pp. 796-801.
[43] S. Venkataramani et al., Substitute-and-simplify: A unied design paradigm for approximate and quality configurable circuits," Proc. DATE, 2013, pp. 796-801.
[44] R. O. Winder, Single Stage Threshold Logic," Switching Circuit Theory and Logical Design, 1961, pp. 321-332.
[45] R. O. Winder, Threshold Logic," 1962, Ph.D. dissertation, Princeton University, Princeton, NJ.
[46] R. O. Winder, Enumeration of Seven-Argument Threshold Functions," IEEE
Transactions on Electronic Computers, 1965, pp. 315-325.
[47] Y. Wu et al., An efficient method for multi-level approximate logic synthesis under error rate constraint," Proc. DAC, 2016. pp. 1-6.
[48] Y. Wu et al., Approximate Logic Synthesis for FPGA by Wire Removal and Local Function Change," Proc. ASP-DAC, 2017. pp. 163-169.
[49] R. Zhang et al., Threshold Network Synthesis and Optimization and its Application to Nanotechnologies," IEEE Transactions Comput-Aided Design Integrated Circuits and Systems, 2005, 24(1):107-18.
[50] Y. Zheng et al., SAT-based Equivalence Checking of Threshold Logic Designs for Nanotechnologies," Proc. Great Lake Symp. VLSI, 2008, pp. 225-230.
[51] http://iwls.org/iwls2005/benchmarks.html