現今人們對於網路的依賴性與日俱增，而網路的使用也隨著科技的進步從有線網路轉變成無線網路，而提及無線網路最容易聯想到的就是生活中隨處可見的Wi-Fi，只需要一個小小的收發基地台，就可以盡情的利用網路滿足個人的需求，因此，對於研究積體電路如何應用於Wi-Fi電路系統中，也是為具實用性與挑戰性的研究題材。本論文提出了具2.8–4.8 GHz調變範圍的三角積分調變之鎖相迴路，主要組成電路有相位頻率偵測器、充電幫浦、三階迴路濾波器、多頻帶之壓控震盪器、具三角積分調變器控制之除頻器，利用運算放大器降低充電幫浦之非理想效應，採用切換式電容對提升電容電感式壓控震盪器之操作頻率範圍，十六位元之三角積分調變器達成所需之除數解析度，以上子電路建立出完整的鎖相迴路架構，此外，本論文提出之應用於Wi-Fi系統之鎖相迴路利用晶圓廠之1P7M的55nm製程模擬設計完成後進行晶片下線，本論文提出之鎖相迴路面積消耗為0.32mm2，消耗功率為24mW，理論除數解析度可達1/65536，操作頻率範圍由64個頻帶所劃分而成，相位頻率鎖定時間為1.25μs。內文開頭為介紹各種鎖相迴路架並且加以比較，接著依序講解鎖相迴路之數學模型、設計流程、提出電路架構之模擬結果、下線晶片的量測考量，最後對於提出之鎖相迴路做統合性的結論。

In recent years, people are increasingly more and more dependent on internet. With the advancement of science and technology, the methods of surfing on the internet turn from wire network to wireless network. When it comes to wireless internet in our daily life, people always associate Wi-Fi. The requirements of everyone can be satisfied by using wireless internet and it merely needs a small router AP. Therefore, it is a practical and challenging study subject that the integrated circuits can be applied to the circuit architecture of the Wi-Fi system.
A delta-sigma phase locked loop with 2.8–4.8 GHz tuning range was proposed in this thesis. The main architecture of proposed PLL is divided in several parts, phase and frequency detector, charge pump, 3rd loop filter, multi-band voltage controlled oscillator, and a divider controlled by delta-sigma modulator. The non-ideal effect of charge pump was reduced by adding a unit gain buffer. The wide tuning range of voltage controlled oscillator was mainly due to six pairs of switched capacitors. The high enough resolution of divisor is fulfilled by 16-bit delta-sigma modulator. The entire architecture of proposed PLL was composed by the circuits mentioned above. In addition, the circuit of proposed PLL was fabricated using a 1P7M 55nm standard CMOS technology and the core circuit occupied an area of 0.32 mm2. The experiment results indicated the total power consumption is 24 mW at 1.2 V supply voltage, the theoretical resolution of the divisor is 1/65536, the range of operation frequency was divided in 64 bands, and the locked time was 1.25 μs.
Besides, the comparison of three kinds of PLLs was as the beginning of this thesis, and the mathematical model of PLLs, the designed flow, the simulation results of proposed circuits, the considerations of measurement were described step by step. Finally, an integrated conclusion for the proposed PLL was given in the last chapter.

中文摘要..........................................................I
Abstract........................................................II
致謝............................................................III
目錄.............................................................IV
圖目錄...........................................................VI
表目錄...........................................................IX
第一章 緒論.......................................................1
1.1動機...........................................................1
1.2章節介紹.......................................................1
第二章 架構介紹與設計原理...........................................3
2.1鎖相迴路介紹...................................................3
2.1.1概述.........................................................3
2.1.2類比式鎖相迴路................................................3
2.1.3數位式鎖相迴路................................................4
2.1.4全數位式鎖相迴路..............................................6
2.1.5鎖相迴路實現架構比較..........................................8
2.2數位式鎖相迴路組成電路介紹......................................10
2.2.1相位頻率偵測器...............................................10
2.2.2充電幫浦....................................................15
2.2.3迴路濾波器..................................................18
2.2.4壓控振盪器..................................................23
2.2.5除頻器......................................................31
2.3理想鎖相迴路設計與參數考量......................................33
2.3.1轉移函式推導................................................33
2.3.2迴路之穩定性................................................36
第三章 非理想效應與雜訊分析........................................41
3.1相位頻率偵測器與充電幫浦死區....................................41
3.2充電幫浦之非理想效應...........................................42
3.3壓控振盪器之相位雜訊...........................................44
3.4鎖相迴路之雜訊.................................................47
第四章 鎖相迴路實現之電路介紹......................................49
4.1相位頻率偵測器與必定重疊電路....................................49
4.2充電幫浦......................................................52
4.3具頻帶切換之壓控振盪器.........................................53
4.4三角積分調變之除頻器...........................................54
4.5三階迴路濾波器.................................................60
第五章 模擬結果...................................................62
5.1相位頻率比較..................................................62
5.2充放電流......................................................64
5.3操作頻帶與相位雜訊.............................................65
5.4三角積分調變器與除頻器除數......................................67
5.5迴路模擬......................................................70
5.6佈局考量......................................................70
第六章 量測......................................................72
6.1量測PCB板設計.................................................72
6.2量測環境介紹..................................................73
6.3量測結果......................................................74
第七章 結論......................................................81
參考文獻.........................................................82

[1]E. Koskin, “Discrete-Time Modelling and Experimental Validation of an All-Digital PLL for Clock-Generating Networks,” in IEEE International Conference on Electronics, Circuit and Systems, Dec. 2016, pp. 434–435.

[2]A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumuolu, “A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider,” IEEE J. Solid-State Circuits, vol. 51, pp. 1771–1784, June 2016.

[3]Z. Wang, C. Huang, and J. Wu, “An ADPLL with a MASH 1-1-1 ΔΣ Time-Digital Converter,” in Mediterranean Electrotechnical Conference, May 2014, pp. 266–270.

[4]Y. C. Huang, and S. I. Liu, “A 2.4GHz Sub-Harmonically Injection-Locked PLL With Self-Calibration Injection Timing,” in IEEE International Solid-State Circuits Conference, April 2012, pp. 338–340.

[5]E. Temporiti, C. W. Wu, D. Baldi, R. Tonietto, and F. Svelto, “A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques,” IEEE J. Solid-State Circuits, vol. 44, pp. 824–834, June 2009.

[6]C. C. Chung, and C. Y. Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE J. Solid-State Circuits, vol. 38, pp. 347–351, Feb. 2003.

[7]W. Z. Chen, and J. T. Wu, “A 2-V, 1.8-GHz BJT Phase-Locked Loop,” IEEE J. Solid-State Circuits, vol. 34, pp. 784–789, Jun 1999.

[8]Y. Sumi, N. Kitai, R. Furuhashi, H. Ishii, Y. Matsuda, and Y. Fukui, “Dead-zones-less Frequency Synhtesizer by Hybrid Phase Detectors,” in Proc. IEEE International Symposium on Circuits and Systems, June. 1999, vol. 4, pp. 410–414.

[9]W. Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” in Proc. IEEE International Symposium on Circuits and Systems, June 1999, vol. 2, pp. 545–548.

[10]H. O. Johansson, “A Simple Precharged CMOS Phase Frequency Detector,” IEEE J. Solid-State Circuits, vol. 33, pp. 295–299, Feb. 2009.

[11]M. V. Paemel, “Analysis of a Charge-Pump PLL: A New Model,” IEEE Transactions on Communications, vol. 42, pp. 2490–2498, Jul. 1994.

[12]T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Sythesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553–559, Feb. 1993.

[13]S. G. Wilson, R. Hale, and C. D. Hsu, “An Inpexpensive Demonstration of Phase-Lock Loop Principles,” IEEE Transactions on Education, vol. 23, pp. 200–204, Nov. 1980.

[14]E. N. Protonotarions, “Pull-In Time in Second-Order Phase-Locked Loops With a Sawtooth Comparator,” IEEE Transactions on Circuit Theory, vol. 17, pp. 372–378, Aug. 1970.

[15]D. T. Hess, “Cycle Slipping in a First-Order Phase-Locked Loop,” IEEE Transactions on Communication Technology, vol. 16, pp. 255–260, April 1968.

[16]林宇亮，《寬頻低雜訊放大器與三角積分調變分數型頻率合成器之研製》，桃園:國立中央大學電機工程研究所碩士論文，2007。

[17]黃博彥，《應用於WiMAX通訊系統之Σ-Δ分數型頻率合成器設計》，桃園:國立中央大學電機工程研究所碩士論文，2007。

[18]高曜煌，《射頻鎖相迴路IC設計》。滄海書局，2005。

[19]劉深淵，楊清淵，《鎖相迴路》。滄海書局，2006。

[20]Behzad Razavi著，李峻霣譯，《類比CMOS積體電路設計(修訂版)》。東華書局，2013。