摘要


系所別：電機工程學系　系統組

論文名稱：具前景式校正機制之10位元1GHz電流引導式數位類比轉換器指導教授：朱大舜 博士
研究生：104061598 魏立帆

隨著通訊系統的進步，數位傳輸的資料量越來越大，也因此類比數位轉換器和數位類比轉換器扮演的腳色越來越重要。而為了符合現今通訊系統的需求，高速、高頻寬和高動態範圍的轉換器將會是未來的趨勢。

本論文主旨主要是在實現一個高速且高頻寬的數位類比轉換器，為了達到高速運作的需求，本文採用電流引導式數位類比轉換器，其速度限制主要來自於輸出端的時間常數(time constant)，方便於高速操作。但其中電流源彼此間的不匹配誤差(Mismatch)，將會影響數位類比轉換器的靜態和動態效能，而為了抵抗Mismatch的影響，除了增加電晶體的大小，我選擇使用另一種方法，利用電流源校正機制，對轉換器上的電流源做校正。在數位類比轉換器運作前，先依靠前景式校正機制，去對每顆電流源做修正，修正後數位類比轉換器再正常運作，由此可以節省電流源的面積，在小面積下就可以達到高精準度的高速數位類比轉換器。

在晶片實現上，本文實現一個10bit數位類比轉換器在65nm製成的環境，在電源電壓2.5V下達到差動輸出0.8V的數位類比轉換器。晶片電路主要可以分為兩架構；數位類比轉換器、三角積分器。數位類比轉換器為電路主體，由電流引導式數位類比轉換器所組成，而三角積分器則是採用一階離散式的三角積分器，主要是用來校正數位類比轉換器上的電流源，使原本未校正前，輸入頻率50M、採樣頻率1GHz的數位類比轉換器的SFDR可以由58db提升到79db。

Abstract

As the communication system advances, the data of the digital transmission is growing rapidly.Therefore, the data converter plays the important role in the recent years. Also, high speed, high bandwidth and dynamic range are the future trend.

The topic of the thesis is implementing the digital to analog converter in the high speed and high bandwidth requirements. For high speed operation, the work employ the current steering data converter which the limit of the speed depends on the time constant, and is convenient in high speed application. However the mismatch between the current sources rigidly influence the static and dynamic performance for the data converter. Except for using bigger size of the device, we use the calibration for the current source instead. Before the operation for DAC, we can adjust the current for the current source one to one in the foreground calibration method which can save the area and also achieve the high accuracy.

In the implementation of the chip, my work employ the 10bit D/A converter in 65nm. The power supply is 2.5V and the differential output’s Vpp is 0.8V. The chip can split in two parts: the D/A converter, the delta sigma ADC. The D/A converter is built by the current steering DAC, and the delta sigma ADC which is used to sample the difference between current source implements in
the first order discrete time delta sigma modulator. After the calibration, SFDR can be improved from 58dB to 79dB in Fin=50M, Fs=1GS/s.

目錄

摘要............................................................i

Abstract(英文摘要)..............................................ii

目錄...........................................................iii

圖目............................................................vi

表目錄...........................................................x


序論.............................................................1

研究動機.........................................................1

論文簡介.........................................................2

第二章 電流引導式數位類比轉換器設計考量.............................3

2.1 簡介.........................................................3

2.2 理想數位類比轉換器............................................3

2.3 電流引導式數位類比轉換器.......................................4

2.3.1 二進碼權重電流引導式數位類比轉換器............................4

2.3.2 溫度計碼電流引導式數位類比轉換器..............................6

2.3.3 R-2R電阻階梯式數位類比轉換器.................................7

2.3.4 分段式電流引導式數位類比轉換器................................8

2.4 電流源架構....................................................9

2.5 Code-Dependent Loading Variation(CDLV)......................10

2.6 Code-Dependent Switching Transients(CDSTs)..................11

2.7 不匹配誤差(Mismatch).........................................14

2.7.1 電晶體不匹配誤差...........................................14

2.7.2 二進碼權重不匹配誤差........................................15

2.7.3 溫度計碼不匹配誤差..........................................16

2.7.4 分段式不匹配誤差............................................17

2.8 電流源布局考量...............................................17

2.9 總結........................................................20

第三章 三角積分器設計考量.........................................22

3.1 Delta Sigma Modulator.......................................22

3.2 Nyquist-rate理論............................................23

3.3 Oversampling理論............................................26

3.4 Noise Shaping理論...........................................26

3.4.1 一階Delta Sigma調變器.....................................27

3.4.2 二階Delta Sigma調變器.....................................27

3.4.3 三階Delta Sigma調變器.....................................28

3.5 穩定度分析..................................................29

3.5.1 李氏準則(Lee’s criterion).................................29

3.5.2 根軌跡(Root locus).......................................30

3.6 離散式一階三角積分器.........................................31

3.6.1 STF、NTF.................................................32

3.6.2 積分器飽和現象............................................33

3.6.3 放大器有限增益............................................33

3.6.4 雜訊分析..................................................35

3.6.5 放大器有限迴轉率..........................................40

3.6.6 採樣開關的非理想效應.......................................41

第四章 電路實現.................................................43

4.1 簡介.......................................................44

4.2 電流源電路..................................................44

4.2.1 LDAC.....................................................45

4.2.2 MDAC.....................................................46

4.2.3 CDAC.....................................................46

4.2.4 FBDAC....................................................47

4.2.5 Mismatch考量.............................................48

4.3 電流源偏壓電路..............................................49

4.4 門閂電路...................................................50

4.5 非重疊時脈產生器............................................51

4.6 同步時序電路................................................53

4.7 溫度計碼解碼器..............................................53

4.8 校正電路....................................................54

4.9 三角積分調變器..............................................55

4.9.1電容選擇...................................................55

4.9.2開關設計...................................................56

4.9.3放大器.....................................................56

4.9.4比較器.....................................................60

4.10校正時序電路................................................61

第五章 模擬結果與佈局量測規劃.....................................63

5.1 靜態參數模擬................................................63

5.2 動態參數模擬................................................64

5.3 晶片佈局....................................................65

5.4 IO規劃.....................................................66

5.5 量測考量....................................................67

5.6 規格整理....................................................68

第六章 結論.....................................................69

6.1 總結........................................................69

6.2 未來展望....................................................69

參考文獻........................................................70

圖目錄

圖1.1 電流源校正機制示意圖........................................1

圖2.1 3bit數位類比轉換器之輸入訊號對類比輸出訊號曲線................4

圖2.2 3bit二進碼權重電流引導式數位類比轉換器.......................5

圖2.3 中間碼突波.................................................6

圖2.4 2bit溫度計碼電流式數位類比轉換器.............................6

圖2.5 2bit R-2R電流式數位類比轉換器...............................8

圖2.6 2-3分段式電流引導式數位類比轉換器............................9

圖2.7 疊接電流源架構.............................................9

圖2.8 阻抗Zo頻率響應............................................10

圖2.9 電流源負載圖..............................................11

圖2.10 電流源切換時的Switching Transients.......................12

圖2.11 電流源切換時Vcs的波動.....................................13

圖2.12 WL、Vov和Mismatch關係圖..................................15

圖2.13 電流源佈局示意圖..........................................18

圖2.14 四象限溫度計碼排列方式....................................19

圖2.15 線性梯度誤差、拋物線梯度誤差...............................20

圖3.1 Delta-Sigma ADC..........................................22

圖3.2 Delta-Sigma Modulator block diagram、Linear model........23

圖3.3 訊號混疊..................................................24

圖3.4量化器…....................................................24

圖3.5 ADC轉換器曲線圖…..........................................24

圖3.6 ADC量化雜訊轉換曲線圖......................................25

圖3.7 功率頻譜密度...............................................25

圖3.8 Oversampling功率頻譜密度...................................26

圖3.9 二階Delta Sigma調變器......................................28

圖3.10 1~3階NTF.................................................29

圖3.11 量化器增益模型............................................30

圖3.12 三階三角積分器NTF之根軌跡..................................30

圖3.13 一階Delta Sigma Modulator................................31

圖3.14 時序圖...................................................31

圖3.15 有限增益.................................................33

圖3.16 有限增益對SNR的影響.......................................35

圖3.17 採樣開關的雜訊............................................36

圖3.18 簡單的單端放大器..........................................36

圖3.19 採樣時的電路雜訊模型.......................................37

圖3.20 積分時的電路雜訊模型......................................37

圖3.21 積分時的等效電路..........................................38

圖3.22 雜訊模型.................................................39

圖3.23 輸出端變化穩定波形圖......................................40

圖3.24開關的切換誤差............................................41

圖4.1系統圖.....................................................43

圖4.2 數位類比轉換器架構圖.......................................43

圖4.3 二進位碼權重LDAC(6bit)....................................45

圖4.4 溫度計碼MDAC(4bit)……......................................46

圖4.5 溫度計碼CDAC(5bit)…….....................................47

圖4.6 二進位碼FBDAC……..........................................48

圖4.7 校正前後的σ_MSB(I).......................................49

圖4.8 電流源偏壓電路............................................50

圖4.9 門閂電路.................................................51

圖4.10 門閂電路輸出訊號.........................................51

圖4.11數位類比轉換器時鐘產生器..................................51

圖4.12 三角積分調變器時鐘產生器.................................52

圖4.13 下板採樣分析圖..........................................52

圖4.14 非重疊時間電路...........................................53

圖4.15 資料傳輸時間圖...........................................53

圖4.16 溫度計碼解碼器...........................................54

圖4.17 校正電路................................................55

圖4.18 放大器..................................................57

圖4.19 輸入端Gm1...............................................58

圖4.20 總增益、相位邊界.........................................59

圖4.21 比較器..................................................60

圖4.22 校正時序電路.............................................61

圖4.23 除二除三電路單元.........................................61

圖4.24 四位元計數器.............................................62

圖4.25 四位元計數器狀態順序.....................................62

圖5.1 Pre-Layout靜態參數模擬結果(未經校正).......................63

圖5.2 Pre-Layout靜態參數模擬結果(經校正).........................63

圖5.3 Post-Layout無mismatch之靜態參數模擬結果....................64

圖5.4 Pre-Layout動態參數模擬結果.................................64

圖5.5 Pre/Post-Layout無mismatch之動態參數模擬結果................65

圖5.6 Pre-Layout SFDR對應Fin之圖表..............................65

圖5.7 晶片佈局圖................................................66

圖5.8 量測模型圖................................................67


表目錄

表2.1 2bit二進位碼轉溫度計碼轉換表...............................7

表2.2 二進位、溫度計碼、分段式比較表.............................21

表4.1 Column(Row)溫度計碼真值表.................................54

表4.2 放大器規格...............................................59

表5.1 數位類比轉換器I/O表單.....................................67

表5.2 Post-Layout數位類比轉換器功率耗損清單.....................68

表5.3 Post-Layout數位類比轉換器規格整理.........................68

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