隨著低密度奇偶檢查(low-density parity-check, LDPC)碼逐漸被廣泛使用，不僅在通訊系統可以看到LDPC碼，在快閃記憶體中也有。於3GPP會期決議在5G行動通訊系統將在資料的傳輸上採用LDPC，並且目標是使傳輸速度高出4G行動通訊系統的10倍，其中採用IR-HARQ的傳輸機制降低LDPC的碼率已提升更正能力，以及為了適應各種資料長度而設定多個循環大小(circulant size)，因此此種高傳輸速度、多碼率、多碼長的要求成為了硬體設計上的困難。另外一方面，先前關快閃記憶體的研究中指出，在TLC NAND快閃記憶體使用非常稀疏的低密度同位檢查碼與非葛雷映射，可以達到與傳統葛雷映射方法相差不多的錯誤率。雖然在疊代式解調與解碼(Iterative Demodulation and Decoding, IDD)接收器中稀疏的LDPC碼可以大幅度降低硬體複雜度，然而相較於傳統非IDD接收器卻會造成解碼器與解調器之間的延遲問題，以及多餘的硬體儲存面積。在本篇論文的第一部分，於FPGA中實現符合5G規格的LDPC編碼器，並且提出取餘數的改良電路，有效的減少硬體延遲時間與硬體使用面積。在本篇論文的第二部分，提出硬體友善交錯結構，有效實現單碼字解碼排程的縱向式IDD接收器，解決IDD接收器中解調器與解碼器之間的閒置問題，並且進一步減少了內部記憶體儲存空間，相較於傳統葛雷非IDD系統與橫向式IDD系統有更好的硬體使用效益與更好的錯誤率表現。

Low-density parity-check (LDPC) codes has been used in mobile communication systems and flash memory. The 3GPP agrees that the LDPC code will be adopted in 5G mobile communication systems, and expects the transmission speed 10 times higher than the 4G mobile communication systems. In flash memory, a very sparse LDPC code was designed for triple-level cell (TLC) NAND flash using non-Gray mapping rule, which is able to achieve a comparable error-rate performance to the conventional Gray mapping-based scheme. Although a sparse LDPC code can be of benefit to hardware implementations of an iterative demodulation and decoding (IDD) scheme, difficulties emerge, such as latency issue between the decoder and demodulator, when compared to non-IDD schemes. In the former part of this thesis, we implemented the LDPC encoder in FPGA. In addition, we proposed the efficient mod module to reduce the hardware delay time and hardware usage area. In the latter part of this thesis, a hardware-friendly structure interleaver is used such that a shuffle-based IDD scheme can be realized efficiently. Comparing to the conventional Gray-based non-IDD scheme and layered-based IDD scheme, the proposed shuffled-based IDD scheme can provide a better hardware efficiency and better error-rate performance.

1. 簡介................................................................................. 1
1.1 動機............................................................................ 1
1.2 論文架構.................................................................... 4
2. 背景回顧......................................................................... 5
2.1 5G NR LDPC校驗矩陣結構與編碼方式............. 5
2.2 使用IDD的LDPC編碼8-PAM系統.......................11
3. 5G NR LDPC 編碼器硬體設計..................................15
3.1 編碼器硬體架構........................................................15
3.2 5G NR LDPC編碼器的合成與驗證結果.............26
4. 縱向IDD系統硬體設計................................................37
4.1 提出之硬體友善腰錯結構......................................39
4.2 縱向式IDD系統硬體結果.......................................41
5. 結論..................................................................................44

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