我的實驗室原本開發的全數位式延遲鎖相迴路編譯器(All-Digital Delay-Locked- Loop Compiler)所使用的鎖相迴路(Delay-Locked-Loop，DLL)電路有兩個顯著的缺點:一是面積大，二是功耗高。這是我的研究首要解決的問題，我接著分析問題並尋找方法加以解決。在經過功率分析後，我得知舊DLL的延遲線(delay line)雖然有極好的解析度(resolution)，但卻使用大量的延遲單元(delay cell)，也是造成大面積與高功耗的原因。為此，我提出了一個新架構，使用較小的面積以及較低的功率消耗，達成同樣的延遲範圍(delay range)。這個新架構被命名為『乒乓型延遲線(Ping-Pong delay line)』。舊的延遲線並聯大量的三態緩衝器(tri-state buffer)來達成高解析度與寬延遲範圍。而我提出的乒乓型延遲線在微調(fine tuning)部分只使用少許的延遲單元以減少面積。為了達到跟舊DLL同樣的延遲範圍，我們使用了兩條相同的延遲線，並讓它們輪流產生輸出訊號。乒乓型延遲線屬於分段式延遲線(segmental delay line)架構，而分段式延遲線在控制碼(control code)切換時，因為切換前與切換後的延遲差，容易產生較大的峰對峰訊號跳動(peak-to-peak jitter)。為了降低跳碼(code jumping)時造成的峰對峰訊號跳動，我使用一個稱為『相位量化器(Phase Quantifier)』的電路。這個電路的功用是將兩個訊號之間的相位差以溫度計碼(thermometer code)量化，藉此使得輸出訊號能在兩條延遲線之間無縫的交換產生，進而避免跳碼造成的峰對峰訊號跳動。最後，我在不同的PVT 條件下驗證這個新DLL的效能。把實驗結果跟前述的並聯三態緩衝器延遲線與傳統的分段式延遲線加以比較，得知乒乓型延遲線能同時在面積、功耗與訊號跳動有不錯的表現。

We have previously developed an all-digital delay-locked-loop (ADDLL) compiler, but its generated instances have two significant issues. One is the large area, and the second is the high power consumption. In this work, it is the foremost problem to solve, and I need to analyze the problem and find a way to solve it. After the power analysis, we can know that the old DLL’s delay line achieves a very good resolution, but it uses many delay cells, which is the cause of large area and high power consumption. To this end, I propose a new architecture, named “ping-pong delay line,” that occupies smaller area and consumes less power, but still achieves the same delay range. The old delay line uses a large number of tristate buffers connected in parallel to achieve high resolution and wide delay range. By fine tuning the proposed ping-pong delay line, only a small number of delay cells are used so as to reduce the area. In order to maintain the same delay range as the old DLL, we use two identical delay lines and let them take turns producing the output signals. The ping-pong delay line belongs to the framework of segmental delay line, while the segmental delay line, in general, is easy to produce a large peak-to-peak jitter when switching control codes. In order to reduce the peak to-peak jitter caused by code jumping, I developed a circuit called “Phase Quantifier” whose function is to quantify the phase difference between two signals with thermometer code. In this way, the output signal can seamlessly exchange between two delay lines, thus avoiding the peak to-peak jitter caused by code jumping. Finally, I verified the performance of DLL in different PVT conditions. Comparing the results with the parallel tristate buffer delay line and traditional segmental delay line, we learned that the ping-pong delay line performs quite well in area, power consumption, and jitter.

Content
摘要 i
Abstract ii
致謝 iii
Content iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 3
Chapter 2 Preliminaries 4
2.1 Previous work 4
2.2 Power analysis 6
2.3 Motivation 7
Chapter 3 Ping-Pong Delay Line 8
3.1 Overall architecture of traditional ADDLL 8
3.2 Overall architecture of ping-pong delay line 9
3.3 Architecture of the delay line 10
3.4 Architecture of the phase detector 17
3.5 Architecture of the phase quantifier 18
3.1 The operation of phase quantifier on ping-pong 22
3.2 DLL Execution Flow 26
Chapter 4 Experimental Results 32
4.1 Waveforms at the typical case 32
4.2 Control transfer from Delay Line A to B 33
4.3 Code jumping by VDD drop 34
4.4 Some key characteristic of proposed DLL 35
4.5 Physical layout of the DLL 36
4.6 Comparison with other works 37
Chapter 5 Conclusion 39
References 40

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