隨著網路的快速發展以及多樣的行動裝置被廣泛應用，資料的傳輸數量呈現了驚人的成長。然而，資料在中央處理器(CPU)和記憶體間交換的過程中，系統會遭遇到資料處理速度不足的問題，我們稱之為馮‧紐曼瓶頸。因此，記憶體內運算就成為了一個具有極大潛力的發展目標，意即能夠使傳統的交換資料過程全部在記憶體內部完成。
記憶體內運算主要的概念包括了減少資料的移動、傳送運算後的結果而非傳出資料使其做運算。因此為了要達到以上的目的，本篇論文的設計概念為在記憶體內加上一些電路，使其具備一些簡單的邏輯功能以達到記憶體內運算的目標。由於目前的瓶頸是記憶體存取的延遲時間，因此利用記憶體內運算可以有效使資料傳輸的延遲被大大地減少。
本篇論文提出了一個以靜態隨機存取記憶體(SRAM)為基礎的記憶體內運算單元，意即可以減少CPU與記憶體間的資料傳輸量以及資料傳輸的能量損耗。此記憶體內運算單元能夠達到一般的SRAM讀寫操作，另外，也可以在一個記憶體周期內實現NAND、OR、XOR、XNOR等邏輯功能。
透過65奈米邏輯製程，本篇論文實現了容量為1Kb之基於SRAM的記憶體內運算單元架構。與先前的論文相比，分別在SRAM模式與記憶體內運算模式中，本篇論文降低了30.4%與15.87%的能量損耗。而量測結果方面，在SRAM模式下，本篇論文達到了0.76ns的量測讀取速度；在記憶體內運算模式下，則是達到了0.9ns的量測讀取速度。

With the rapid development of the network and the widely popular of variety mobile devices, the number of data transmission has had amazing growth. However, in the process of data exchange between CPU and memory unit, the system suffers the issue of insufficient speed of data processing called von Neumann bottleneck. Therefore, computing-in-memory, which makes the traditional data exchange process being done inside the memory, becomes a great potential development target.
The main concept of computing-in-memory includes reducing the data movement and transferring the result data after computing instead of transferring data to compute. In order to achieve the target above, the design concept is adding some circuits in the memory, makes it to be provided with some simple logic functions to achieve the goal of computing-in-memory. Since the current bottleneck is the latency of storage, it makes the data transfer delay dramatically reduced by using computing-in-memory.
Here, we propose a cell based on SRAM to achieve computing-in-memory, which can reduce data transmission and energy consumption between CPU and memory unit. This cell is able to achieve a general SRAM read/write operation, in addition, it is able to compute NAND, OR, XOR and XNOR functions within a single memory cycle.
Based on 65nm CMOS logic process, we fabricate a 1Kb computing-in-memory cell array based on SRAM. This work achieves 30.40% and 15.87% lower energy consumption in SRAM-mode and computing-mode respectively than previous work. For measurement results, this work achieves 0.76ns measured access time in SRAM-mode and 0.9ns measured access time in computing-mode.

摘要 i
Abstract ii
致謝 iv
Contents v
List of Figures vii
List of Tables ix
Chapter 1 Introduction 1
1.1 The Role of Memory in SoC products 1
1.2 Memory Landscape 2
1.2.1 RAM 4
1.2.2 CAM 5
1.2.3 ROM 5
1.2.4 Programmable NVMs 6
1.3 Von Neumann bottleneck 7
1.4 Computing-In-Memory (CIM) 8
Chapter 2 Background 10
2.1 Characteristic of ReRAM 10
2.1.1 Structure of ReRAM 10
2.1.2 ReRAM Operation 12
2.2 Characteristic of 6T SRAM cell 13
2.2.1 Structure of SRAM 13
2.2.2 Write Operation 15
2.2.3 Read Operation 15
Chapter 3 Previous Work 17
3.1 Crossbar Array Based CIM 17
3.2 1T1R ReRAM Based CIM 19
3.3 4+2T SRAM Based CIM 21
Chapter 4 Proposed Circuit Schemes and Analysis 26
4.1 Proposed Computing-In-Memory Circuit Scheme 26
4.1.1 Cell Structure 26
4.1.2 Operation 28
4.2 Analysis and Comparison 33
4.2.1 Speed Comparison 33
4.2.2 Energy Comparison 36
Chapter 5 Macro Implementation 39
5.1 Floor Plan of CIM-SRAM Macro 39
5.2 Design for Testchip 40
Chapter 6 Experimental Results and Conclusion 42
6.1 Measured Performance 42
6.2 Conclusions and Future Work 50
Reference 52

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