自旋力矩轉移-磁阻式隨機存取記憶體(STT-MRAM) 是目前新興之非揮發性記憶體，因為其高速存取、高耐久性、非揮發性三大優勢，被認為是目前極具發展潛力之新興記憶體。在目前記憶體階層中，儲存裝置以快閃記憶體為主，不過因其低存取速度，及低耐久性，使之與主記憶體之動態存取記憶體存在效能落差，將會造成記憶體系統之效能瓶頸。而新興之記憶體概念”儲存級記憶體(SCM)”作為儲存裝置及主記憶體間溝通之橋梁，自旋力矩轉移-磁阻式隨機存取記憶體將在此新領域中扮演重要之角色。
在次碩士論文中將探討自旋力矩轉移-磁阻式隨機存取記憶體在讀取上會面臨之挑戰，並提出一電壓感測放大器電路解決以下問題，以提升讀取效能:
1. 自旋力矩轉移-磁阻式隨機存取記憶體之穿隧式磁阻比例(TMR-Ratio)小及製程飄移現象，造成資料0與資料1之阻值差異性小，造成讀取良率低落。
2. 自旋力矩轉移-磁阻式隨機存取記憶體元件阻值偏低，造成位元線放電到地速度過快，感測範圍無法拉開至足夠電壓差，造成讀取良率低落。
3. 過高讀取電壓容易造成讀取干擾(Read disturb)現象，而傳統方案在低讀取電壓下讀取良率低落。
因此，我們提出具製程變異容忍及預放大感測裕度之連續紀錄並增強電壓感測放大器 (CRE-VSA)。在台積電28奈米製程模擬分析下，我們提出的CRE-VSA的相較於傳統電壓感測放大器可容忍6.3倍以下之TMR-比例，並可容忍2倍以下之讀取電壓，並相對傳統電流及傳統電壓讀取在相同讀取良率下減少80%及34%的能量消耗，並可放大5.85倍感測裕度及在不同位元線長短下增進1.5至1.86倍讀取速度。
我們與台積電合作並以28奈米製程實作32Kb STT-MRAM記憶體晶片，在正常操作電壓0.9V下，量測提出之電路讀取速度為1.3 ns而傳統電路讀取速度為1.86ns，增進1.43倍讀取速度。而提出之電路最低讀取電壓為140mV而傳統放大器為280mV，可容忍2倍更低之讀取電壓。最後量測提出電路之電壓偏移為15mV而傳統感測放大器為65mV，可以達到4.3倍感測裕度之放大。

Spin Torque Transfer- Magnetoresistive Random Access Memory (STT-MRAM) is a promising emerging memory candidate for several reasons, high speed accesses, high endurance and non-volatility. In current memory system hierarchy. The performance gap is occurring between main memory (DRAM) and storage (flash memory) due to slow access speed and low endurance of flash memory. The performance gap will cause memory system performance bottleneck. A new memory concept, storage class memory (SCM), which as the bridge between storage memory and main memory. STT-MRAM will play an important role in this new area.
In this paper, we discuss the issue of STT-MRAM in reading, and proposed a voltage mode sense amplifier to solve the following problems to improve the read performance:
1. The low TMR-ratio of STT-MRAM cell and process variation effect, resulting in small resistance difference between data-0 and data-1. Therefore, leading to low sensing yield.
2. The low resistance value of STT-MRAM cell will cause the bit line discharge to ground too rapid to generate enough voltage difference between BL and BLB, resulting in low sensing yield.
3. High read voltage causes read disturb issue. However the conventional scheme suffers low sensing yield at low read voltage operation.
Therefore, we propose a Continuous-Recording-and-Enhancement Voltage-Mode Sense Amplifier (CRE-VSA) with the Process Variation Toleration and Pre Amplify Sensing Margin Scheme to solve the above reading issue. Under tsmc 28 nm technology analysis, our proposed CRE-VSA achieves 6.3x larger tolerance TMR ratio at a given R¬P, and achieves 2x lower read voltage than conventional scheme. Moreover, CRE-VSA can achieve 80% and 34% lower read energy than typical current-mode and CNV-VSA at the same sensing yield. In addition, CRE-VSA achieves 5.85x sensing margin enhancement and CRE-VSA achieve 1.5x~1.86 faster read access time (TAC) than conventional VSA at different BL length.
We cooperate with tsmc and implement our proposed sensing scheme at tsmc 32kb 28nm STT-MRAM macro. At typical VDD=0.9V, measured access time of CRE-VSA is 1.3ns and conventional VSA is 1.86ns, proposed scheme can improve 1.43x read access time. Measured minimum read voltage of CRE-VSA is 140mV and conventional VSA is 280mV, this scheme can tolerate 2x lower read voltage. Finally, the measured offset of CRE-VSA is 15mV and conventional is 65mV, this work achieves 4.3x sensing margin enhancement.

致謝 i
摘要 ii
Abstract iv
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 The Role of Memory in SoC products 1
1.2 Memory Hierarchy 2
1.3 Challenges of Flash Memory 4
1.4 Emerging Non-Volatile Memories 7
Chapter 2 Characteristic of STT-MRAM 11
2.1 Introduction of MRAM 11
2.2 Read and Write Operations 13
2.3 Recent Development 16
Chapter 3 Design Challenges of STT-MRAM Read 19
3.1 Structure and Operations of Conventional Sensing Schemes 19
3.2 Voltage and Current Type Sense amplifier Comparison for STT-MRAM 21
3.3 Design Challenges 23
3.3.1 Threshold Voltage in Process 23
3.3.2 Issues of STT-MRAM 24
3.4 Previous Arts 25
Chapter 4 Proposed Circuits Schemes and Analysis 29
4.1 Proposed Sense Amplifier 29
4.1.1 Motivation and Concept of Proposed Sense Amplifier 30
4.1.2 Structure of Proposed Sense Amplifier 33
4.1.3 Operations of Proposed CRE-VSA 34
4.2 Analysis and Comparison 38
4.2.1 Efficiency of Margin Enhancement 38
4.2.2 Tolerance of low TMRMIN and Read Voltage 41
4.2.3 Read Energy Consumption Reduction 43
4.2.4 Capacitor analysis 44
4.2.5 Access time (TAC) Improvement 46
Chapter 5 Measurement Results and Conclusion 47
5.1 STT-MRAM Macro 47
5.2 Design for Testchip 49
5.3 Measurement results 51
5.4 Conclusions and Future Work 57
Reference 60

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