生醫植入式晶片越來越受到大家的重視，但隨著科技的發展與新的製程技術，往往都會朝向更低的電壓環境邁進，但是對於深層腦部刺激而言神經刺激電路必須要能夠輸出足夠大的電壓才能達到有效的治療效果，因此就會在刺激器的驅動電路端會有電晶體無法承受刺激電路所需要的高電壓進而有崩潰的現象發生，文獻上有幾種不同的解決方法，本論文採用了改變標準元件結構設計的結合淺矽溝槽汲極延伸式電晶體，用來耐受高壓並減少刺激端電路設計的複雜度而且因為在標準製程下實現，也更容易和其他生醫系統一併進行整合。
本文提出一個在標準0.18 μm 1.8V / 3.3 V CMOS製程下基於結合淺矽溝槽汲極延伸式電晶體設計的多模神經刺激器，分為兩個重點，一開始會先從分析到從測試鍵中逐步地建立起耐高壓元件的模型，建立模型的結果也和實際量測結果僅有5%之誤差而且此元件可以耐受到8V的電壓環境，並將其使用在刺激器的電路設計上。
除了基於高壓元件的刺激電路設計，第二個重點是通常功能性電刺激治療的方式都是使用固定的電壓或者電流刺激刺激，此論文中的多模式刺激晶片能夠分別產生多種不同類型的刺激方式，電壓，電流和電荷式刺激，並將不同的刺激合併在同一個電路上。在電壓模式下，電壓的範圍可以從2.81V至7.46V，電流模式下的範圍則可以從11.6μA至666μA，電荷模式下範圍則可以從10.42nC至495nC，總晶片不含PAD的面積僅有0.11mm2，除了面積減少的優勢之外，不同的刺激方式也可以在研究上用來探討能達到什麼不一樣的治療效果。

For biomedical applications, it is important to minimize the power consumption and to be implemented in a compact size therefore low-voltage CMOS technologies is preferred. However, neural stimulators must deliver high energy to the stimulation tissue load hence a high voltage will across it. To prevent the reliability issues and transistors breakdown, lots of methods have been used. But in order to be integrated in the standard CMOS process, the STI-DEMOS which changes the structure of standard MOSFET is adopted and can be integrate on the SOC much more easily with lower cost.
This paper presents a high-voltage device based multi-mode neural stimulator compatible with the standard 0.18μm 1.8 V/3.3 V CMOS process. The high-voltage tolerant device STI-DMOS is fabricated and use to prevent transistors from some oxide over-stress, junction breakdown and reliability issues. And the model of STI-DMOS is also build from the measurement results of test-keys and the fitting results in modeling are acceptable at five percentage error. From the measurement result, the high voltage device work will and it can sustain up to 8V voltage.
Besides, most of Functional electrical stimulation (FES) preferred the use of constant voltage or current stimulation. And, the stimulator in this thesis is able to produce three different types of basic stimulation signal, voltage, current and switched-capacitor stimulation respectively. The stimulus signal can range from 2.81V to 7.46V in voltage mode, 11.6μA to 666μA in current mode and 10.42nC to 495nC in charge mode with the STI-DMOS device. The total core area of the chip occupies only 0.11mm2.

摘 要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
ABSTRACT. . . . . . . . . . . . . . . . . . . . . . . . . . . .ii
致 謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
目 錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
圖 目 錄. . . . . . . . . . . . . . . . . . . . . . . . . . . .vi
表 目 錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . x
第一章 緒論. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究背景. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究動機與目的. . . . . . . . . . . . . . . . . . . . . . . 2
1.3 章節簡介. . . . . . . . . . . . . . . . . . . . . . . . . . 3
第二章 文獻回顧. . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 疊接式耐高壓驅動電路. . . . . . . . . . . . . . . . . . . . .4
2.2 CMOS製程下的耐高壓元件. . . . . . . . . . . . . . . . . . . .4
2.3 神經刺激電路. . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 陰陽極校正電路. . . . . . . . . . . . . . . . . . . . . . . .7
第三章 標準製程之結合淺矽溝槽汲極延伸式電晶體之量測與建模. . . . .9
3.1 結合淺矽溝槽汲極延伸式電晶體結構. . . . . . . . . . . . . . .9
3.1.1 結合淺矽溝槽汲極延伸式N型電晶體量測資料 . . . . . . . . . . 11
3.1.2 結合淺矽溝槽汲極延伸式P型電晶體量測資料 . . . . . . . . . . 14
3.2 有無淺矽溝槽汲極延伸式電晶體量測結果之比較 . . . . . . . . . .17
3.3 結合基底偏壓之可變電阻建模預測 . . . . . . . . . . . . . . . 19
3.3.1 結合淺矽溝槽汲極延伸式N型電晶體之模型 . . . . . . . . . . . 20
3.3.2 結合淺矽溝槽汲極延伸式P型電晶體之模型 . . . . . . . . . . . 27
3.4 小結 . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
第四章 多模式神經刺激電路設計 . . . . . . . . . . . . . . . . . .34
4.1 多模式神經刺激電路架構與規格 . . . . . . . . . . . . . . . . .34
4.1.1 多模式神經刺激電路的電流刺激操作模式 . . . . . . . . . . . . 36
4.1.2 多模式神經刺激電路的電壓刺激操作模式 . . . . . . . . . . . .39
4.1.3 多模式神經刺激電路的電荷刺激操作模式 . . . . . . . . . . . .42
4.2 電路模擬結果 . . . . . . . . . . . . . . . . . . . . . . . .47
4.2.1 晶片佈局圖 . . . . . . . . . . . . . . . . . . . . . . . .47
4.2.2 電流刺激模式電路模擬表現 . . . . . . . . . . . . . . . . . 47
4.2.3 電壓刺激模式電路模擬表現 . . . . . . . . . . . . . . . . . 48
4.2.4 電荷刺激模式電路模擬表現 . . . . . . . . . . . . . . . . . 49
4.3 電路量測 . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3.1 量測環境 . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3.2 晶片量測結果 . . . . . . . . . . . . . . . . . . . . . . .52
4.3.3 電路模型預測結果與晶片量測結果比較 . . . . . . . . . . . . .60
4.3.4 結合耐高壓元件之多模式刺激電路與疊接耐壓電路之比較 . . . . . 61
4.4 總結與文獻對比 . . . . . . . . . . . . . . . . . . . . . . .63
第五章 結論與未來展望 . . . . . . . . . . . . . . . . . . . . . 65
參考文獻 . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

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