因為成本效益比靜態隨機存取記憶體高且隨機存取速度較快閃記憶體更為快速之優點，內嵌式動態隨機存取記憶體廣泛地應用於電子產品、穿戴性裝置以及物聯網之應用。
因為電晶體具有漏電流之關係，內嵌式動態隨機存取記憶體需要週期性地做刷新維持所儲存的資料。然而刷新的動作越頻繁，功率消耗則越大。基於這個原因，低功率消耗之設計在內嵌式動態隨機存取記憶體便變得十分重要。最直接降低功率消耗的方式就是降低額定電壓，然而將內嵌式動態隨機存取記憶體操作於低電壓則需要考慮記憶胞之資料保存時間會短於操作於高電壓之問題。
為了使內嵌式動態隨機存取記憶體操作於低電壓之環境，我們提出資料警覺之感測放大器增加記憶胞儲存之電荷，因此可以增加感測裕值使得在低壓時可以讀出正確資料，進而降低在自我刷新時所耗損之功率。
我們在內嵌式動態隨機存取記憶體晶片中實現此提案，於台積65奈米標準CMOS製程下製造。量測結果顯示對於低壓操作部分，於室溫下的環境下可以比傳統再低70毫伏正常運作，並減少功率消耗。

Embedded DRAMs are commonly used in many electronic products, wearable devices and Internet of Thing application because of its lower cost than SRAM and its faster random access than FLASH memory.
Due to the MOSFET native leakage characteristic, embedded DRAM needs to refresh with a fixed period to maintain stored data. The more frequent refresh operation does, the more power consumes. For this reason, low power design is significant in embedded DRAM design. The direct method to reduce power consumption is scaled down the supply voltage, but operation in low supply voltage, the cell data retention time will shorter than data retention time in high supply voltage.
To solve this problem, we propose a Data-Aware Sense Amplifier to extend data retention time in lower voltage condition. With capacitor boosting operation, this sense amplifier increases charge stored in cell capacitor so as to enlarge margin in sensing phase achieves to read out data correctly in low voltage mode, and reduces power consumption in self-refresh mode.
A Data-Aware Sense Amplifier is implemented in an embedded DRAM macro, which is fabricated in TSMC 65nm Generic CMOS process. The measurement result shows that 70mV lower supply voltage can be achieved at room temperature in low supply voltage operation.

Chapter 1 1
1.1 Low Power Embedded-DRAM Applications 1
1.2 Challenges of Low Power Embedded DRAM 2
1.3 Overview of This Thesis 4
Chapter 2 5
2.1 Embedded DRAM Description 5
2.2 Structure of Embedded DRAM 6
2.3 Write Operation 8
2.4 Read Operation 10
2.5 Refresh Operation 12
Chapter 3 14
3.1 Cell Structure 14
3.1.1 Capacitor Structure 16
3.1.2 Gain Cell 17
3.2 Data Retention Time 17
3.3 Leakage Mechanisms 18
3.3.1 Sub-threshold Current (I1) 19
3.3.2 Gate-Induced Drain Leakage (I2) 20
3.3.3 Gate-Oxide Tunneling Current (I3) 21
3.3.4 Hot carrier injection Current 22
3.3.5 Reverse-Biased Junction BTBT Current 23
3.3.6 Punch-Through Current (I6) 23
3.4 Power Consumption 23
3.5 Previous Work 24
3.5.1 Low-voltage sensing and write-back scheme 24
Chapter 4 26
4.1 Motivation of Proposed Sense Amplifier 26
4.2 Proposed Sense Amplifier 27
4.2.1 Structure of Proposed Sense Amplifier 27
4.2.2 Sensing Operations 28
4.3 Analyses of Proposed Sense Amplifier 31
4.3.1 Sense Margin Enhancement 32
4.3.2 Power Reduction in Operation Mode 33
4.3.3 Yield Analysis 34
4.3.4 Refresh Period 36
4.3.5 Capacitor Analysis of Proposed Sense Amplifier 38
Chapter 5 39
5.1 Macro of Embedded DRAM 39
5.1.1 Memory Cell Arrays 40
5.1.2 Peripheral Circuits 41
5.2 Design for Test Chip 42
Chapter 6 43
6.1 Measurement Results 43
6.2 Conclusions and Future Work 46

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