非揮發性記憶體在現今的儲存記憶體市場上蔚為風潮。尤其是快閃記憶體更在近年來已然成為非揮發性記憶體的主流。快閃記憶體具有高密度、低成本及低耗能的特性，使得它擁有市場競爭力。然而，快閃記憶體需要高電壓來進行寫入和消除資料，而且其操作速度偏慢，顯然無法達到下世代產品的需求。除此之外，快閃記憶體在製程微縮時會遭遇到需要克服的問題，像是耦合雜訊干擾和高偏移臨界電壓等。相較之下，新興非揮發性記憶體只需要較低的操作電壓就能達到更好的效能。因此，他們有能力成為下世代非揮發性記憶體的主宰。
一些新興非揮發性記憶體(例如: 電阻式記憶體、磁阻式記憶體)非常適合用於需要快速讀取和低供給電壓的內嵌式裝置應用上，特別是使用電池的穿戴式裝置。然而，在大容量的非揮發記憶體中，低阻值率和阻值高偏移的現象會對感測造成一些問題。
為了解決由低阻值率和偏低的阻值造成的問題，我們提出一個利用雙參考電流取代傳統中點參考電流的距離競速架構來增強原本偏小的裕度，並且在位元線電流較大的情況下能抑制感測放大器的輸入偏移。在大位元線電流下能抑制等效偏移達傳統的2.5~3倍。而且，我們提出的架構在長位元線的情況下能有1.2~1.6倍的速度提升，讀取良率也可以改善30%以上。
我們用容量為1Mb的電阻式記憶體來驗證我們提出的架構，此晶片使用台積電的65奈米標準CMOS製程。在供給電壓為一伏且位元線長度為512個時，量測到的讀取時間為3.6奈秒。

Non-volatile memory (NVM) is very popular on storage memory market nowadays. Especially, Flash memory has already been the mainstream of NVM in recent years. The characteristics of Flash memory, such as high density, low cost, and low energy consumption, make it competitive on the market. However, Flash memory requires high voltage to program and erase, and the operation speed is still too slow to catch up with the requirements of next-generation inventions. Besides, there are some challenges which have to be overcome for the scaling of Flash memory, like coupling noise and large variation of threshold voltage. On the other hand, emerging non-volatile memories require lower operating voltage and have higher performance than Flash memory. Therefore, emerging NVMs have the ability to take over the next-generation NVMs.
Some emerging NVMs (i.e. ReRAM or MRAM) are suitable for high performance and low supply voltage embedded applications, particularly for wearable devices with batteries. Nevertheless, the small R-ratio and high variation make some problems on sensing NVM devices in large capacity.
So as to overcome the issues caused by small R-ratio and small LRS resistance, we propose a distance-racing read scheme to enhance the small margin by dual reference instead of conventional mid-point reference and suppress the input offset of sense amplifier under large BL current. The equivalent offset suppression of proposed scheme is 2.5~3x smaller than conventional works under large BL current. Moreover, the proposed scheme can achieve 1.2~1.6x faster speed than conventional works in long BL. In addition, the read yield can also be improved at least 30% in long BL.
Finally, our proposed scheme is verified in a 1Mb ReRAM macro fabricated in TSMC 65nm CMOS process. The measured access time of ReRAM macro is 3.6ns at typical VDD = 1V and BL-length = 512.

摘要 i
Abstract ii
致謝 iv
Contents v
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 The Memory Landscape 1
1.2 Challenges of Flash Memory 5
1.3 Emerging Non-Volatile Memories 9
1.3.1 PCM 9
1.3.2 MRAM 10
1.3.3 FeRAM 12
1.3.4 ReRAM 13
Chapter 2 Characteristic of Contact-ReRAM 17
2.1 Structure of Contact-ReRAM 17
2.2 Write Operation 19
2.3 Read Operation 21
2.4 Distribution of Contact-ReRAM 22
Chapter 3 Design Challenges of Small Window Sensing 23
3.1 Design Challenges 23
3.1.1 Threshold Voltage in Process 23
3.1.2 Issues of Small R-ratio Devices 25
3.2 Conventional Current Type Sense Amplifier 27
3.3 Previous Arts 29
Chapter 4 Proposed Scheme and Analysis 35
4.1 Proposed Sense Amplifier 35
4.1.1 Concept of Proposed Sense Amplifier 35
4.1.2 Structure of Proposed Sense Amplifier 39
4.1.3 Operation of Proposed Sense Amplifier 40
4.2 Analysis and Comparison 45
4.2.1 Offset Comparison 45
4.2.2 Speed Comparison 47
4.2.3 Yield Comparison 49
Chapter 5 Measurement Results and Conclusion 51
5.1 ReRAM Macro 51
5.2 Design for Test 53
5.3 Measured Performance 56
5.4 Conclusions and Future Work 61
Reference 64

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