隨著現代CMOS電路的複雜性和密度越來越高，由參數和製程偏移所引起的電路缺陷越來越難以被檢測。其中單元認知測試（CAT）方法已被提出並且用於產生更貼近於真實情況地邏輯單元內部缺陷的測試向量約束。可以透過將這些約束提供給邏輯閘級自動化測試向量產生器（Gate-level ATPG）來增加故障模型涵蓋率。在本論文的第一個方法中，我們提出了更高效的CAT測試流程，大大地減少了在單元層級上以CAT流程所產生之測試向量。在原始CAT中，利用詳盡的晶體管級電路模擬找到適當的測試向量是被認為是非常耗時的。為了解決這個問題，首先，我們使用傳統的開關級自動化測試向量產生器（SL-ATPG）取代之，實驗表明它可以非常有效地產生CAT流程中的測試向量。第二，基於面向佈局的缺陷模型生成方法，我們提出了一種自動將這些缺陷模型注入到以標準元件為基礎的開關式網絡結構中的演算法。第三，傳統的ATPG主要是基於固定式(Stuck-at)和切換式(transition)的故障模型，這種方式很難找到微小的電路延遲缺陷。然而，利用觀察電路中的短路電流可能可以檢測到這類型的電路缺陷。因此我們提出了基於檢測電路中短路電流路徑是否存在的向量生成方法。最後，我們比較了原始的CAT與使用SL-ATPG取代後，詳細電路模擬的模擬時間。該實驗使用商業化的180nm CMOS標準單元元件庫。結果表明，利用SL-ATPG取代之方法可以將模擬時間成功地減少約403倍。
然而，許多不存在於關鍵路徑上並且難以檢測之缺陷可以輕易地從CAT等所有常規測試方法中逃脫出來。本文討論的第二種方法是為了進一步提升測試品質，我們引入了群體感知（QS）方法進行電路測試（感應），以提高測試可靠度。與傳統的IDDQ測試、老化測試和壓力測試不同，群體熱感知（TQS）方法可以引發以熱能為基礎的連鎖反應，並且放大其微小的電路偏差，透過的觀察單元的群體行為來判斷整體電路狀態。該實驗基於商業的45nm CMOS標準單元元件庫，並通過ISCAS s9234電路進行驗證。結果表明，當注入的微小缺陷數大於489時，有搭配TQS的電路總電流將高於2.08mA，相較於未搭配TQS的電路較容易檢測出微小的電路偏差。本文提出的TQS測試方法結合了壓力測試、IDDQ測試和帶有分佈式熱能傳感器的自我感知能力。與其他最先進的或傳統的測試方法相比，群體感知可以幫助提高測試品質，為電路測試提供新的測試觀點。

With the increasingly high complexity and density of modern CMOS circuit, defects caused by parametric and process variations, e.g., are more and more difficult to be detected. The Cell-Aware Test (CAT) methodology has been proposed to generate more realistic input conditions of the cells, which target the cell-internal defects. One can increase the fault coverage by feeding these conditions to the gate-level ATPG. In the first approach of this thesis, we propose an efficient test flow for CAT to drastically reduce the time for CAT-enhanced test generation at the cell level. In the original CAT, the detailed transistor-level circuit simulation is used to find appropriate test patterns, and it has been considered as very time consuming. To solve this problem, first, we exploit the conventional Switch-Level ATPG (SL-ATPG), and experimentally show that it can efficiently generate test patterns in the CAT flow. Second, based on layout-oriented defect generation method, we propose an algorithm to automatically inject those defects into the switching network used in SL-ATPG, for cells in the standard library. Third, note that the traditional ATPG is primarily based on the stuck-at-fault and transition-fault models, it is difficult to find small-delay defects. However, the same defects are likely to be detected by observing the short-circuit current, so we propose current-based checks for a pattern generation method which are able to detect the existence of a short-circuit path. Finally, we compare the simulation time of detailed circuit simulation and that of SL-ATPG in CAT. The experiment is based on a commercial 180nm CMOS standard cell library. The result shows that the SL-ATPG method can successfully reduce the simulation time by about 403X.
However, many hard-to-detect defects not located on the critical path can easily escape from all the conventional testing methods including the CAT. The second approach discussed in this thesis is that, in order to further reduce the defect level, we introduce the quorum sensing (QS) methodology to circuit testing (sensing) for improving the quality and reliability. Different from the traditional IDDQ test, burn-in test and stress test, the thermal quorum sensing (TQS) method provoke a thermal chain reaction to expose the subtle variations in the circuit, which can be observed by the common cell population behavior. The experiment is based on a commercial 45nm CMOS standard cell library, and it is verified by the ISCAS s9234 benchmark. The results show that, when the number of small defects injected is more than 489, the difference in total current will be higher than 2.08mA, which can easily be detected. The proposed TQS test methodology combines the stress test, the IDDQ test, and the self-sensing capability by the distributed thermal sensors. Compared with other state-of-the-art or traditional testing methods, quorum sensing can enhance the test quality, providing a new perspective into circuit test.

Abstract i
List of Figures v
List of Tables vi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Introduce of Cell-Aware Test 2
1.3 Introduce of Quorum Sensing 3
1.4 Approach and Result 4
1.5 Organization 4
Chapter 2 Switch-Level ATPG-Based Cell-Aware Test 6
2.1 Previous Works 6
2.2 Proposed Methodology 8
2.3 Defect Injection 10
2.4 Test Pattern Generation 14
Chapter 3 The Thermal Quorum Sensing Approach 17
3.1 Quorum Sensing Models 17
3.2 Thermal Quorum Sensing Strategy 20
3.3 Quorum Sensor Design 25
3.4 Simulation Flow and Methodology 29
3.4.1 Detailed Simulation Flow 31
3.4.2 Circuit Simulation 32
3.4.3 Thermal Domain Simulation 33
3.4.4 Sensor Behavior Simulation 37
3.4.5 Defect Injection 38
Chapter 4 Experimental Result 39
4.1 Results for SL-ATPG-Based Cell-Aware Test 39
4.1.1 Results for Short Defects 40
4.1.2 Results for Open Defects 41
4.2 Results for Thermal Quorum Sensing Approach 43
4.2.1 Comparison of Experimental Results 45
Chapter 5 Conclusion and Future Work 48
5.1 Conclusion 48
5.2 Future Work 49
Bibliography 50

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