本研究利用電子槍蒸鍍系統(E-gun system)沉積多晶矽(poly-Si)與高密度電漿化學氣相沉積系統(HDP-CVD)沉積非晶矽薄膜製作保護層於本實驗室已證明能強化基板強度之奈米結構上，藉以保護奈米結構並且降低基板翹曲。
利用金屬輔助化學蝕刻(Metal-Assisted Chemical Etching)而蝕刻出之奈米結構能分散矽基板之應力，並提升基板之強度，而此優異的特點能解決矽基板不能承受高功率原件材料氮化鎵(GaN)在磊晶時因晶格不匹配而產生過大應力造成破片的疑慮。但因奈米結構約深4 μm、寬100 nm之高深寬比結構容易附著微粒造成後續製程與機台之汙染，所以CVD (Chemical Vapor Deposition)以一複合矽/二氧化矽材料覆蓋之，其中二氧化矽之晶格常數小於矽而導致超過15 μm甚至50 μm之翹曲，且再後續製程會被清洗液腐蝕而導致附蓋保護層剝落，對正面溫度敏感度高之氮化鎵磊晶薄膜造成直接影響，影響面積超過50％。
本實驗利用E-gun system以物理氣相沉積(Physical Vapor Deposition)之方式沉積多晶矽，其後再以HDP-CVD沉積非晶矽保護薄膜，大幅降低翹曲度最低至4 μm並且不會有氧化物影響磊晶之性質。以此實驗提供一新型基板於氮化鎵磊晶，期望能降低破片率提升產能並精進磊晶品質。

In this study we use E-gun deposition system to deposit poly-Si thin film and HDP-CVD deposited amorphous silicon as a protection layer on the nanotexture which our group has already proved can strengthen the Silicon substrate.
The protection layer can provide that the nanotexture not been damaged and lower the bow of the substrate. We use Metal-Assisted Chemical Etching method to create the nanotexture which disperse the stress on the substrate which can elevate the strength of the wafer to endure the high stress caused by the epitaxy layer of GaN for high power devices. With the nanotexture created by the Metal-Assisted Chemical Etching we can save the wafer from cracking, but due to the high aspect ratio (4 μm high and width for 100 nm) of the nanotexture it may catch particles which is contamination for the later process and facilities. We make a composite material by chemical vapor deposition in order to protect the nanotexture and prevent the contamination problems, but it still exist many flaw such as oxide contamination or over bowing from 15 μm to over 50 μm.
This experiment by using physical vapor deposition by E-gun system and HDP-CVD system, we can derive a poly-Si/a-Si layer which reduce the over bow to 4 μm and will not influence the epitaxy process by oxide. This experiment provide a new strengthening substrate which can lower the cracking rate for a higher productivity.

圖目錄 vi
表目錄 x
第一章 前言 1
1.1 研究背景 1
1.2氮化物成長於矽基板之簡介 5
1.3提升氮化鎵成長於矽基板品質之應力消彌技術 8
1.4基板強度提生技術 11
1.4.1常見之矽基材強化方法 11
1.4.2矽基板之奈米化強化技術 17
1.5研究動機 22
1.6論文架構 24
第二章 理論與原理 25
2.1脆性材料力學 25
2.1.1 脆性材料之抗折強度 26
2.1.2 奈米強化應力分散理論 28
2.2製程理論 34
2.2.1金屬輔助化學蝕刻技術 34
2.2.2物理氣相沉積保護層 38
2.2.3 高密度電漿化學氣相沉積系統(High Density Plasma-enhanced Chemical Vapor Deposition) 43
第三章 實驗規劃 45
3.1實驗設計與流程 45
3.2以金屬輔助化學蝕刻製備矽(111)奈米結構 50
3.3保護層材料之優化與製備 51
第四章 實驗結果 53
4.1 保護層材料之選擇與沉積 53
4.2 抗腐蝕奈米結構保護層 63
4.3 交叉汙染量測 66
4.4 晶邊奈米結構之移除 71
4.5 強度量測 75
第五章 結論 81
第六章 未來工作 83
附錄 94
附錄A. 掃描式電子顯微鏡 94
附錄B. 高真空型掃描試探針顯微鏡 95
附錄C. 晶圓翹曲量測儀 97
附錄D. SIMS偵測原信號強度原始數值陳列 99
附錄E.近年奈米結構強化程度比較 100

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