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作者(中文):鄒承諺
作者(外文):Tsou, Cheng-Yen
論文名稱(中文):以修正型能量密度法評估晶圓級封裝之可靠度
論文名稱(外文):Reliability Assessment of Wafer Level Package using Modified Energy Based Model
指導教授(中文):江國寧
指導教授(外文):Chiang, Kuo-Ning
口試委員(中文):李昌駿
劉德騏
鄭仙志
口試委員(外文):Lee, Chang-Chun
Liu, De-Shin
Cheng, Hsien-Chie
學位類別:碩士
校院名稱:國立清華大學
系所名稱:動力機械工程學系
學號:104033559
出版年(民國):106
畢業學年度:105
語文別:中文
論文頁數:77
中文關鍵詞:晶圓級晶片尺寸封裝溫度循環測試升降溫速率持溫時間潛變Darveaux能量密度法修正型能量密度法(Max’s model)Coffin-Manson應變法元素網格大小
外文關鍵詞:Wafer Level Chip Size Packaging (WLCSP)Thermal Cycling Testramp ratedwell timecreepDarveaux’s modelmodified energy based modelCoffin-Manson’s modelmesh size
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近年來,為了達到消費者對於消費性電子產品的需求,電子封裝技術朝向微小化、輕量化、高功率以及多功能進行發展。封裝結構從原先傳統的接腳式(Lead Frame)型態轉變為球閘陣列封裝(Ball Grid Array, BGA),如晶圓級晶片尺寸封裝(Wafer Level Chip Scale Packaging, WLCSP)與覆晶封裝(Flip Chip)。WLCSP與Flip Chip封裝最主要的差異在於封裝結構中是否有應力緩衝層設計。WLCSP封裝結構其晶片及錫球間有緩衝層設計,因此WLCSP型態的封裝並不需要以填充底膠的方式來提升可靠度。緩衝層設計的目的是藉由減緩由熱膨脹係數不匹配所造成的熱應力來達到增加封裝結構可靠度之目的。產品上市前必須通過一系列的封裝結構可靠度測試實驗,其中溫度循環測試(Temperature Cycling Test, TCT)為一標準且被廣泛運用的可靠度測驗,能否通過溫度循環測試為電子封裝產業的一個重要的課題。不過可靠度測驗是費時且需花費大量資金的,若能以有限元素法(Finite Element Method, FEM )對WLCSP進行壽命的初步預估,能減少因溫度循環測試造成的多餘花費並縮短產品上市的時間。
本研究利用有限元素模擬軟體ANSYS®建立二維WLCSP模型,針對結構中錫銀銅焊料合金(SnAg3.0Cu0.5, SAC305)受不同溫度循環測試進行錫球壽命的探討。對於錫球壽命預估的模擬,應力集中現象導致有限元素網格尺寸對模擬結果產生影響,須利用體積權重的概念進行網格大小的選定,在固定網格大小的前提進行錫球壽命預估。
當模擬不同升降溫速率以及持溫時間的溫度負載,與時間相依的潛變行為是需要被考慮的,不同溫度負載下材料受應變率影響,應力-應變曲線會隨著負載不同而改變,同時考量到應力、應變的能量法如Darveaux能量密度法和修正型能量密度法是本研究選擇用來預測潛變行為下錫球之壽命預估公式。在升降溫速率及持溫時間固定時,可只考量塑性行為並忽略潛變效應,因為塑性行為是與時間不相依的,只考量塑性行的模擬不僅能減少電腦運算量,也能避免因潛變實驗數據的不確定性造成壽命預估的誤差產生,最終將模擬應變增量帶入Coffin-Manson應變法和修正型能量密度法進行壽命預估探討。
本研究在固定錫球材料的前提下,針對三種壽命預估公式進行驗證,考量到潛變效應,Darveaux能量密度法和修正型能量密度法搭配與之對應的錫球元素網格大小,模擬結果與實驗結果之誤差都能在一定的範圍,其中修正型能量密度法有較高的準確性;考量塑性行為的Coffin-Manson應變法與修正型能量密度法也能有合理的壽命預估。

關鍵詞:晶圓級晶片尺寸封裝、溫度循環測試、升降溫速率、持溫時間、潛變、Darveaux能量密度法、修正型能量密度法(Max’s model)、Coffin-Manson應變法、元素網格大小。
In recent years, electronic packaging has developed to achieve small form, lighter weight, high power and more functionality because of the costumer’s demand. Therefore, electronic packaging has developed from conventionally lead frame to ball grid array such as flip chip and WLCSP. The major difference between WLCSP and flip chip is stress buffer layer. WLCSP does not need underfill protection because it possesses a soft stress buffer layer between silicon chip and solder bump. The purpose of buffer layer is to improve the reliability of the solder ball which is due to the coefficient of thermal expansion (CTE) mismatch between the chip and the substrate. Before mass production, the products have to pass the reliability test. Thermal cycling test is one of the standard reliability tests and has been widely used for testing long term reliability of packaging components. Make sure the electronic products can pass the thermal cycling test become a key issue to electronic packaging industry. To meet the time-to-market and long term reliability requirements, using finite element to predict a precise life cycle of solder joints becomes the main trend of electronic packaging product development.
In this study, A 2-D dimensional finite element model is built to simulate the WLCSP with SAC305 solder joints which is under different thermal loading. When WLCSP is under different ramping rate and dwell time, the creep behavior which is time dependent should be considered. The stress- strain curve will be changed due to different ramp rate and dwell time. Therefore, Darveaux’s model and modified energy based model are selected to investigate the reliability of WLCSP since they both consider the strain and stress. If ramp rate and dwell time are fixed, we decide to simulate the model with different maximum and minimum temperature. Consider plastic behavior not only plastic behavior is time independent but also to reduce computing time. After getting simulation results, we predict the SAC305 solder joint life cycle by substituting plastic strain into Coffin-Manson’s model.
Three prediction models have preliminarily verified. When considering creep behavior, the difference between test results and simulation results are both in a certain range based on the optimal mesh size. In my preliminary study, modified energy based model can provide a better reliability life prediction than Darveaux’s model. The life prediction using Coffin Manson’s model is also resonable.

Keywords: Wafer Level Chip Size Packaging (WLCSP), Thermal Cycling Test, ramp rate, dwell time, creep, Darveaux’s model, modified energy based model, Coffin-Manson’s model, mesh size
摘要...I
ABSTRACT...III
目錄...V
圖目錄...VIII
表目錄...X
第一章 緒論...1
1.1 研究動機...1
1.2 文獻回顧...3
1.3 研究目標...11
第二章 基礎理論...13
2.1 錫球外型預估...13
2.2 有限元素法基礎理論...15
2.2.1 線彈性有限元素法理論...16
2.2.2 材料非線性理論...20
2.2.3 數值方法及收斂準則...25
2.3 硬化法則...26
2.3.1 等向硬化法則...27
2.3.2 動態硬化法則...27
2.4 潛變理論...28
2.4.1 Garofalo-Arrhenius潛變模型...29
2.4.2 Anand模型...31
2.5 封裝結構可靠度預測方法...34
2.5.1 Coffin-Manson應變法...34
2.5.2 Darveaux能量密度法...35
2.5.3 修正型能量密度法(Max’s model)...36
第三章 WLCSP溫度循環測試及有限元素模型...37
3.1 WLCSP於溫度循環測試...37
3.2 WLCSP有限元素模型建立...41
3.3 材料參數設定...49
3.4 基本假設及邊界條件設定...51
3.5 溫度負載設定...52
第四章 初步成果與討論...54
4.1 WLCSP在塑性下之壽命預估...54
4.1.1 實驗與有限元素模型驗證...54
4.1.2 修正壽命預估公式...60
4.2 WLCSP在潛變下之壽命預估...61
4.2.1 實驗與有限元素模型驗證...62
4.2.2 修正壽命預估公式...66
4.2.3 網格尺寸與修正型能量密度法之探討...67
第五章 結論與未來展望...70
參考文獻...74

[1] L. F. Coffin, “A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal,” Transactions ASME, Vol. 76, pp. 931-950, 1954.
[2] S. S. Manson, Thermal stress and low cycle fatigue, New York: McGraw-Hill, 1966.
[3] R. Darveaux, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” Journal of Electronic Packaging, Vol. 124, pp. 147-154, 2002.
[4] 吳凱強,先進封裝錫球接點於不同溫度循環負載速率下之可靠度評估,國立清華大學動力機械工程學系,博士論文,2016.
[5] R. Tummala, Fundamentals of Microsystems Packaging: McGraw Hill Professional 1st edition, 2001.
[6] C. M. Liu, C. C. Lee, and K. N. Chiang, "Enhancing the Reliability of Wafer Level Packaging by using Solder Joints Layout Design," IEEE Transactions on Component and Packaging Technologies, vol. 29, pp. 877-885, 2006.
[7] T. T. Mattila, H. Xu, O. Ratia, and M. Paulasto-Krockel, "Effects of thermal Cycling Parameters on Lifetimes and Failure Mechanism of Solder Interconnections," 60th Electronic Components and Technology Conference, Las Vegas, NV, USA, June 1-4, 2010.
[8] J. Lau, and W. Dauksher, “Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints,” Electronic Components and Technology Conference 55th, Lake Buena Vista, FL, USA May 31 -June 3 2005.
[9] 李至軒,潛變行為對晶圓級封裝之可靠度影響分析,國立清華大學動力機械工程學系,碩士論文,2015.
[10] L. Hua, T. Tilford, and D. R. Newcombe, “Lifetime Prediction for Power Electronics Module Substrate Mount-Down Solder Interconnect,” International Symposium on International Symposium on High Density Packaging and Microsystem Integration, pp. 1-6, Shanghai, China, Jun. 26-28, 2007.
[11] J. G. Lee, and K. N. Subramanian, “Effects of TMF Heating Rates on Damage Accumulation and Resultant Mechanical Behavior of Sn–Ag Based Solder Joints,” Microelectronics Reliability, Vol. 47, pp. 118-131, 2007.
[12] L. Anand, “Constitutive Equations for Hot-Working of Metals,” International Journal of Plasticity, Vol. 1, pp. 213-231, 1985.
[13] H. J. Frost, and M. F. Ashby, Deformation Mechanism Maps, Pergamon Press, 1982.
[14] E. P. Busso, M. Kitano, and T. Kumazawa, “A Visco-Plastic Constitutive Model for 60/40 Tin-Lead Solder Used in IC Package Joints,” Journal of Engineering Materials and Technology, Vol. 114, pp. 331-337, 1992.
[15] M. J. Pfeifer, “Solder Bump Size and Shape Modeling and Experimental Validation,” IEEE Transactions on Components, Packaging and Manufacturing Technology – Part B,Vol. 20, No.4, pp. 452-457,1997.
[16] S. M. Heinrich, M. Schaefer, S. A. Schroeder and P. S. Lee, “Prediction of Solder Joint Geometries in Array-Type Interconnects,” ASME Journal of Electronic Packaging, Vol. 118, pp. 114-121,1996
[17] K. N. Chiang and W. L. Chen, “Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array,” Transactions on Journal of Electronic Packaging, Vol. 120, No. 2, pp,175-178, 1998.
[18] K. A. Brakke, The Surface Evolver, Experimental Mathematics, Vol.1, No.2, pp. 141-165, 1992.
[19] K. A. Brakke, Surface Evolver Manual, version 2.01 Minneapolis, MN: The Geometry Center, 1996.
[20] K. A. Brakke, “The Surface Evolver and the Stability of Liquid Surfaces” Philosophical Transactions: Mathematical Physical and Engineering Sciences, Vol. 354, pp. 2143-2157, 1996.
[21] L. Li and B.H. Yeung, “Wafer Level and Flip Chip Design Through Solder Prediction Models and Validation,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 650-654, 2001.
[22] B. H. Yeung and T. Y. T. Lee, “Evaluation and Optimization of Package Processing, Design, and Reliability through Solder Joint Profile Prediction,” IEEE Electronic Components and Technology Conference, pp, 925-930, Orlando, Florida, USA, May 29 – June 1, 2001.
[23] K. N. Chiang and C. A. Yuan, “An Overview of Solder Bump Shape Prediction Algorithms with Validations,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 2, pp. 156-162, 2001.
[24] K. J. Bathe, Finite Element Procedures in Engineering Analysis, Prentice Hall, 1982.
[25] C. L. Dym, and I. H. Shames, Solid Mechanics: A Variational Approach, Augmented Edition: Springer, 2013.
[26] R. D. Cook, D. S. Malkus, M. E. Plesha, and R. J. Witt, Concepts and Applications of Finite Element Analysis 4th, Wiley, 2001.
[27] W. N. Findley, J. S. Lai, and K. Onaran, Creep and relaxation of nonlinear viscoelastic materials, with an introduction to linear viscoelasticity, Amsterdam ; New York : North-Holland Pub. Co. : sole distributors for the U.S.A. and Canada, Elsevier/North Holland, 1976.
[28] W. Dauksher, “A Second-Level SAC Solder-Joint Fatigue-Life Prediction Methodology,”,IEEE Transactions on Device and Materials Reliability, Vol. 8, no. 1, pp. 168-173, 2008.
[29] J. Chakrabarty, Theory of Plasticity 3th, Butterworth-Heinemann, 2006.
[30] N. E. Dowling, Mechanical Behavior of Materials: Engineering Methods for Deformation, Fracture, and Fatigue, Upper Saddle River, New Jersey: Prentice-Hall, Inc, 1999.
[31] G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, “Applying Anand Model to Represent the Viscoplastic Deformation Behavior of Solder Alloys,” ASME Journal of Electronic Packaging, Vol. 123, pp. 247-253, 2001.
[32] S. B. Brown, K. H. Kim, and L. Anand, “An Internal Variable Constitutive Model for Hot Working of Metals,” International Journal of Plasticity, Vol. 5, pp. 95-130, 1989.
[33] F. Garofalo, Fundamentals of Creep and Creep-Rupture in Metals, New York: Macmillan Company, 1965.
[34] Y. J. Xu, L. Q. Wang, F. S. Wu, W. S. Xia, H. Liu, “Effect of Interface Structure on Fatigue Life under Thermal Cycle with SAC305 Solder Joints,” IEEE Electronic Packaging Technology International Conference, pp, 959-964, Aug 11-14, 2013.
[35] M. Motalab, M. Mustafa, J. C. Suhling, J. Zhang, J. Evans, M. J. Bozack and P. Lall, “Thermal Cycling Reliability Predictions for PBGA Assemblies That Include Aging Effects,” ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, Vol.1 , Burlingame, California, USA, July 16–18, 2013.
[36] M. C. Hsieh and S.L. Tzeng, "Solder Joint Fatigue Life Prediction in Large Size and Low Cost Wafer-Level Chip Scale Packages," International Conference on Electronic Packaging Technology(ICEPT) , pp. 496-501, Chengdu, China , May 2014.
[37] M. C. Hsieh, "Modeling Correlation for Solder Joint Fatigue Life Estimation in Wafer-Level Chip Scale Packages," International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 65–68, Taipei, Taiwan , Oct. 2015.
[38] B. Rogers and C. Scanlan, "Improving WLCSP Reliability Through Solder Joint Geometry Optimization", International Symposium on Microelectronics, Vol. 2013, pp. 546-550, 2013.
[39] J. Chang, L. Wang, J. Dirk, and X. Xie, “Finite Element Modeling Predicts the Effects of Voids on Thermal Shock Reliability and Thermal Resistance of Power Device,” Welding Journal , Vol. 85, pp. 63-70, 2006.
[40] P. T. Vianco, Fatigue and Creep of Lead-free Solder Alloys: Fundamental Properties, Chapter 3 Lead-free Solder Interconnect Reliability, Edited by D. Shangguan, ASM International, pp. 67-106, 2006.
[41] K. N. Chiang, H. C. Cheng, and W. H. Chen, "Large-Scaled 3-D Area Array Electronic Packaging Analysis", Journal of Computer Modeling and Simulation in Engineering, Vol. 4, No.1, pp.4-11, 1999.
[42] M. Spraul, W. Nuchter, A. Moller, B. Wunderle, and B. Michel, “Reliability of SnPb and Pb-free flip–chips under different test conditions,” Microelectronics Reliability, Vol. 47, pp. 252-258, 2007.
 
 
 
 
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