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作者(中文):楊承曄
作者(外文):Yang, Cheng-Yeh
論文名稱(中文):分子束磊晶成長氧化鉿/砷化鎵之介面及其電性研究
論文名稱(外文):Interfacial Electrical Properties of MBE-HfO2/GaAs MOS capacitors
指導教授(中文):郭瑞年
洪銘輝
指導教授(外文):Kwo, Ray-Nien
Hong, Ming-Hwei
口試委員(中文):蘇雲良
陳仕鴻
學位類別:碩士
校院名稱:國立清華大學
系所名稱:物理學系
學號:104022537
出版年(民國):107
畢業學年度:106
語文別:英文
論文頁數:87
中文關鍵詞:三五族半導體砷化鎵氧化鉿金氧半電容熱穩定性介面缺陷密度
外文關鍵詞:lll-V semiconductorGaAsHfO2MOSCAPthermal stabilityDit
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在這研究中,我們直接成長分子束磊晶的氧化鉿在未使用介面鈍化層或經化學處理的砷化鎵基板上。並且使用原子層化學氣相沉積的氧化鋁作為保護層沉積在氧化鉿上避免水氣吸收。將樣品進行系統性地退火並量測電容電壓特性,樣品呈現良好的電容電壓特性並擁有低的介面缺陷密度以及高的熱穩定性。在p型基板的金氧半電容退火條件為在氮氣環境300度 10分鐘550度10分鐘,接著在氦氣環境進行900度60秒高溫退火,而在n型基板的金氧半電容退火條件為在氮氣環境550度20分鐘,接著在氦氣環境進行900度30秒高溫退火。將樣品在400度使用混合氣體退火5分鐘,p型基板的金氧半電容在聚積區域的頻率分散(500Hz-1MHz)為5%,n型基板的金氧半電容則為11.9%。
此外,使用準靜態電容電壓量測技術萃取出來的介面缺陷密度在中間能隙附近無峰型分佈。在中間能隙位置的介面缺陷密度為4.7×1011 eV-1cm-2,最低的介面缺陷密度的值為1.4×1011eV-1cm-2落在價電帶上方0.3電子伏特的位置。而使用電導方法所量測出來的介密缺陷密度在價電帶上方0.35電子伏特的位置為1.8×1011eV-1cm-2。在這研究中,有著低介面缺陷密度以及高熱穩定性的的氧化鉿/砷化鎵系統有著很高的潛力能做出具有出色表現的砷化鎵金氧半電晶體
In this study, MBE-HfO2 was in-situ deposited on freshly-grown GaAs without using interfacial passivation layers and chemical treatments. An ALD-Al2O3 film was subsequently deposited on MBE-HfO2 as a protecting layer against moisture from atmosphere. Systematic annealing process is adopted to samples and shows excellent C-V characteristics with low Dit and high thermal stability. The MOSCAPs of MBE-HfO2/GaAs were initially post deposition annealed at 300oC 10min 550oC 10min in N2 followed by 900oC 60s in He for p-type and 550oC 20min in N2 followed by 900oC 30s in He for n-type. The MOSCAPs were further improved by post metallization annealing at 400oC 5min in forming gas, which has shown small frequency dispersion 5.8% (500Hz-1MHz) at accumulation region for p-MOSCAPs, and 11.9% for n-MOSCAPs. Furthermore, Dit spectrum extracted from QSCV method showed no peak profile near midgap region. The Dit near midgap region is given by 4.7×1011eV-1cm-2 and a minimum value of 1.4×1011eV-1cm-2 located at 0.3eV above valence band edge is observed. The Dit value of 1.8×1011eV-1cm-2 located at 0.35eV above valence band edge is given by conductance method. The high thermal stability and low interfacial trap density attained in this experiment shows the high potential of MBE-HfO2/GaAs system to realize high performance enhance mode GaAs MOSFETs.
Table of Content.............................................VI
中文摘要......................................................IX
Abstract......................................................X
Table Captions..............................................XII
Figure Captions...........................................XIIII
Chapter 1 Introduction........................................1
1.1 Background................................................1
1.2 High-κ Dielectrics on III-V Compound Semiconductors.......6
1.3 Motivation................................................9
Chapter 2 Theory and Instrumentations........................11
2.1 MBE System...............................................11
2.1.1 Molecular Beam Epitaxy (MBE)...........................11
2.1.2 Reflection High Energy Electron Diffraction (RHEED)....13
2.2 Atomic Layer Deposition..................................14
2.3 Metal-Oxide-Semiconductor (MOS) capacitor................16
2.3.1 Electrical measurement.................................16
2.3.2 Ideal C-V Characteristics..............................18
2.3.2 Different Types of Oxide Charges.......................22
2.4 Extraction of Interfacial Trap of Densities..............24
2.4.1 Terman Method..........................................24
2.4.2 Quasi-static Capacitance-Voltage (QSCV) Measurement....24
2.4.3 Conductance method.....................................26
2.5 Extraction of Electrical Parameters from C-V Curves......28
2.5.1 Substrate Doping Concentration.........................28
2.5.2 Flat-Band Voltage (VFB)................................29
3.1 Film Deposition in UHV Multi-Chamber system..............31
3.1.1 Sample Preparation.....................................31
3.1.2 III-V Semiconductor Layers Deposition..................32
3.1.3 Oxide Deposition.......................................33
3.2 Annealing Treatment......................................34
3.3 Electrical Properties Measurement........................35
Chapter 4 Result and Discussion..............................37
4.1 Electrical Characteristics of GaAs MOSCAPs Passivated by MBE Deposition HfO2..............................................37
4.1.1 Medium Temperature Annealing Effect on MBE-HfO2/p-GaAs.37
4.1.2 Low Temperature Annealing Effect and the Duration at Medium Temperature Annealing Effect on MBE-HfO2/p-GaAs..............45
4.1.3 C-V Characteristics of MBE-HfO2/p-GaAs(001) under Various High temperature Annealing Condition.........................51
4.1.4 Effect of Annealing at Different Temperature...........56
4.1.5 C-V Characteristics of MBE-HfO2/GaAs(001) under Various Annealing Condition..........................................59
4.2 Comparison of MBE-HfO2, MBE-Y2O3 and ALD-Y2O3 on GaAs in C-V and Dit distribution.........................................64
Chapter 5 Conclusion.........................................69
References...................................................72

1. Gordon E. Moore, Electronics 38, 114 (1965)
2. http://en.wikipedia.org/wiki/Moore's_law
3. S. Thompson, IEDV Technical Digest, p.61, (2002)
4. R. H. Dennard et al., IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, 1974
5. Y. Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. D. Ye, IEEE Int. Electron Devices Meet. 323 (2009).
6. H. C. Chiu, T. D. Lin, P. Chang, W. C. Lee, C. H. Chiang, J. Kwo, Y. S. Lin, Shawn.S. H. Hsu, W. Tsai, and M. Hong, 2009 Intl. Symposium on VLSI Technology, Systems and Applications (’09 IEEE VLSI-TSA), Proceedings of Technical Program, pages 141-142 (2009), Hsinchu, Taiwan, April 27-29, 2009.
7. G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations”, J. of Appl. Phys. 89, 5243 (2001).
8. Y. Taur, IEEE Spectrum, p. 25-29, (1999)
9. J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors”, Rep. Prog. Phys. 69, 327 (2006)
10. Hiroshi Iwai, Ultimate CMOS scaling, nano-KISS (2013).
11. International Technology Roadmap for Semiconductors (ITRS), 2010 Update. http://www.itrs.net/
12. M. W. Hong, J. R. Kwo, P. C. Tsai, Y. C. Chang, M. L. Huang, C. P. Chen, and T.D. Lin, “III-V MOSFET’s with High k Dielectrics”, Jpn. J. of Appl. Phys. 46, 316 7(2007).
13. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M.Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N.Mukherjee, W. Rachmady, U. Shah, and Robert Chau, “Advanced High-k Gate Dielectric for High-performance Short-Channel In0.7Ga0.3As Quantum Well FET on Si for Low Power Logic Application”, Tech. Dig. - Int. Electron Devices Meet.319 (2009).
14. M. Heyns and W. Tsai, “Ultimate Scaling of CMOS Logic Devices with Ge and III-V Materials”, MRS Bull. 34, 485 (2009).
15. S. M. Sze and Kwok K. Ng, “Physics of Semiconductor Devices”, 3rd edition, John Wiley & Sons, Inc., Hoboken, New Jersey, USA 2007.
16. J. Robertson and B. Falabretti, “Band offset of high k oxides on III-V semiconductors”, J. Appl. Phys. 100, 014111 (2006).
17. K. Navrátil, I. Ohlídal, and F. Lukeš, “The physical structure of the interface between single-crystal GaAs and its oxide film”, Thin Solid Films 56, 163 (1979).
18. G. P. Schwartz, “Analysis of native oxide films and oxide-substrate reactions on III–V semiconductors using thermochemical phase diagrams”, Thin Solid Films.103, 3 (1983).
19. W. T. Tsang, “Self‐terminating thermal oxidation of AlAs epilayers grown on GaAs by molecular beam epitaxy”, Appl. Phys. Lett. 33, 426 (1978).
20. E. I. Chen, N. Holonyak, and S. A. Maranowski, “AlxGa1−xAs–GaAs metal–oxide semiconductor field effect transistors formed by lateral water vapor oxidation of AlAs”, Appl. Phys. Lett. 66, 2688 (1995).
21. A. G. Revesz and K. H. Zainnger, “An Amorphous Modification of Gallium-Arsenic (V) Oxide”, J. Amer. Ceram. Soc. 46, 606 (1963).
22. O. A. Weinreich, “Oxide Films Grown on GaAs in an Oxygen Plasma”, J. Appl. Phys. 37, 2924 (1966).
23. M. Hong, J. P. Mannaerts, J. E. Bowers, J. Kwo, M. Passlack, W.-Y. Hwang, and L. W. Tu, “Novel Ga2O3(Ga2O3) passivation techniques to produce low Dit oxide-GaAs interfaces”, J. Cryst. Growth 175, 422 (1997).
24. J. Kwo, D. W. Murphy, M. Hong, R. L. Opila, J. P. Mannaerts, A. M. Sergent, and R. L. Masaitis, “Passivation of GaAs using (Ga2O3)1−x(Gd2O3)x, 0 ⩽ x ⩽ 1.0 films”, Appl. Phys. Lett. 75, 1116 (1999).
25. M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, “Epitaxial cubic gadolinium oxide as a dielectric for gallium arsenide passivation”, Science, 283, 1897 (1999).
26. E. J. Kim, L Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, “Border traps in Al2O3 In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals”, Appl. Phys. Lett. 96, 012906 (2010).
27. T. D. Lin, Y. H. Chang, C. A. Lin, M. L. Huang, W. C. Lee, J. Kwo, M. Hong, “Realization of high-quality HfO2 on In0.53Ga0.47As by in-situ atomic-layer-deposition”, Appl. Phys. Lett. 100, 172110 (2012).
28. Y. Xuan, Y. Q. Wu, and P. D. Ye, “High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1A/mm”, IEEE Electron Device Lett. 29, 294 (2008).
29. H. Zhao, J. Huang, Y.-T. Chen, J. H. Yum, Y. Wang, F. Zhou, F. Xue, and J. C. Lee, “Effects of gate-first and gate-last process on interface quality of In0.53Ga0.47As metal-oxide-semiconductor capacitors using atomic-layer-deposited Al2O3 and HfO2 oxides”, Appl. Phys. Lett. 95, 253501 (2009).
30. Y. C. Chang, M. L. Huang, K. Y. Lee, Y. J. Lee, T. D. Lin, M. Hong, J. Kwo, T. S. Lay, C. C. Liao, and K. Y. Cheng,”Atomic-layer-deposited HfO2 on In0.53Ga0.47As :Passivation and energy-band parameters”, Appl. Phys. Lett 92, 072901 (2008).
31. K. Y. Lee, Y. J. Lee, P. Chang, M. L. Huang, Y. C. Chang, M. Hong, and J. Kwo, “Achieving 1 nm capacitive effective thickness in atomic layer deposited HfO2 on In0.53Ga0.47As”, Appl. Phys. Lett. 92, 252908 (2008).
32. N. Goel, D. Heh, S. Koveshnikov, I. Ok, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M. Yakimov, Y. Sun, P. Pianetta, C. K. Gaspe, M. B. Santos, J. Lee, P. Majhi, and W. Tsai, “Addressing The Gate Stack Challenge For High Mobiltiy InxGa1-xAs Channels For NFETs”, Tech. Dig. - Int. Electron Devices Meet. 363 (2008).
33. Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, “High performance submicron inversion-type E-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics”, Tech. Dig. - Int. Electron Devices Meet. 637 (2007).
34. T.D.Lin, APPLIED PHYSICS LETTERS 103, 253509 (2013
35. M.Hong, APPLIED PHYSICS LETTERS 111, 123502 (2017)
36. Y. C. Chang, APPLIED PHYSICS LETTERS 102, 093506 (2013)
37. K. Mistry et al., IEEE IEDM, 247, (2007)
38. S. M. George, A. W. Ott, and J. W. Klaus, “Surface Chemistry for Atomic Layer Growth”, J. Phys. Chem. 100, 13121 (1996).
39. R. L. Puurunen, “Surface chemistry of atomic layer deposition: A case study for the trimethylaluminum/water process”, J. Appl. Phys. 97, 121301 (2005).
40. S. M. Sze, and K. K. Ng, Physics of Semiconductor Device, Wiley-Interscience (2007).
41. L. M. Terman, “An investigation of surface states at a silicon dioxide interface employing metal-oxide-silicon diodes”, Solid State Electron. 5, 285-299 (1962)
42. C. N. Berglund, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.ED-13, No. 10, (1966).
43. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
44. Roy Winter, Winter et al.: New method for determining flat-band voltage J. Vac. Sci. Technol. B 31(3), May/Jun 2013
45. Yu Kai Su, “Thesis: Interfacial Electrical Properties of MBE-Y2O3/GaAs MOS capacitors”, (2013).
46. T. W. Chang et al, Microelectron. Eng. 178, 199 (2017)

 
 
 
 
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