本論文主要研究多晶GeSn無接面薄膜式電晶體的元件特性及可靠度之研究與探討。同時建立相關理論及製程手法來改善元件特性及可靠度。首先在第二章中，第一部份針對Sn濃度為5.1％的多晶GeSn薄膜結晶性與退火溫度的相依性進行分析，同時也討論SiO2覆蓋層對於多晶GeSn薄膜的影響。探討完最佳之薄膜結晶性後，第二部份探討多晶GeSn薄膜厚度對於無接面薄膜式電晶體的元件特性影響。在第三章中，為再進一步提高薄膜的結晶性，利用各種不同的退火氣體環境來探討對於多晶GeSn薄膜結晶性的影響，同時並探討無接面電晶體的元件特性、晶粒尺寸和通道缺陷密度之相依性。在第四章中，採用Ar氣體退火的多晶GeSn 無接面薄膜式電晶體作為基礎，再進一步探討電漿處理對於元件特性與可靠度的影響。其中Ar氣體退火搭配NH3電漿處理提高了最多的多晶GeSn無接面薄膜式電晶體之元件特性，這主要歸因於較低的介面缺陷密度和通道缺陷密度。在第五章中，基於改善的元件性能，多晶GeSn無接面薄膜式電晶體結合HfZrOx鐵電材料來進行研究與探討。其中鐵電材料的可靠度可以透過NH3電漿處理處理和插入Ta2O5介面層來進行改善。在改善了HfZrOx鐵電材料的可靠度之後，對多晶GeSn無接面薄膜式鐵電記憶體進行了突觸行為應用與評估，包括短期增強作用、長期增強作用、長期抑制作用和脈衝時序依賴可塑性行為。在第六章中，我們通過金屬-鐵電-半導體結構來探討鐵電材料在多晶GeSn薄膜和磊晶GeSn薄膜上之鐵電特性與可靠度之差異。其中通過矽(111)基板上的磊晶之GeSn薄膜與鐵電材料具有更好的介面品質，而使其具有較佳的鐵電特性及可靠度。

This thesis focuses on the investigation of device and reliability performance for poly-GeSn thin film transistors (TFTs). We develop theories and processes to reinforce device performance and reliability. After the introduction in Chapter 1, the effect of annealing temperature and SiO2 capping layer on the crystallinity of poly-GeSn film with Sn concentration of 5.1% is investigated by various physical analyses in Chapter 2. Based on the best crystallinity, the impact of channel thickness on JL TFTs devices performance is explored by electrical analyses. To further improve the crystallinity of poly-GeSn film, the effects of annealing gas ambient on grain size, channel defect density and consequent device electrical characteristics are studied in Chapter 3. In Chapter 4, poly-GeSn JL TFTs with Ar gas annealing are employed as the vehicle to explore how plasma treatments affect device performance and reliability. NH3 plasma treatment is found to be effective in improving poly-GeSn device performance, mainly resulting from lower defect density of bulk and channel defect density. In Chapter 5, based on the enhanced device performance, poly-GeSn JL TFTs gated with ferroelectric HfZrOx materials are well investigated. The reliability of ferroelectric TFTs (Fe-TFTs) can be achieved by using NH3 plasma treatment and inserting an interfacial layer of Ta2O5. Then the Fe-TFTs are evaluated for synaptic device applications including STP, LTP, LTD and STDP behaviors. In Chapter 6, by using metal-ferroelectric-semiconductor (M-F-S) structure as the platform, the correlation between substrate crystallinity (polycrystalline GeSn or epitaxial GeSn) and the quality of ferroelectric HfZrOx film is explored. Finally, conclusions of this work and further recommendations to improve the device performance are made.

Contents
摘要 i
Abstract ii
Acknowledgement iii
Contents iv
Table Lists xviii
Chapter 1 Introduction 1
1-1 Background and Motivation 1
1-2 Three-Dimensional Integrated Circuits (3D-IC) 2
1-3 Junctionless Structure 4
1-4 Advantages of GeSn materials 5
1-5 Ferroelectric Materials 6
1-6 Organization of the Thesis 7
1-7 References 10
Chapter 2 Investigation of Layer Thickness and Capping Layer on Characteristics of Poly-GeSn Junctionless P-Channel Thin Film Transistors 21
2-1 Introduction 21
2-2 Experiment 23
2-3 Results and Discussion 25
2-3-1 Effect of GeSn Layer Thickness on Device Performance 25
2-3-2 Impact of Capping Layer for Films Crystallinity 26
2-3-3 Impact of Capping Layer for Film Concentration 27
2-3-4 Effect of Capping Layer on Device Performance 28
2-3-5 Effect of Global and Local Capping Layer on Device Performance 28
2-3-6 Impact of Capping Layer on Surface Roughness 29
2-3-7 Impact of Capping Layer on Contact Resistivity 30
2-3-8 Effect of Global and Local Capping Layer on Mobility 32
2-4 Summary 32
2-5 References 34
Chapter 3 Implementing P-channel Junctionless Thin Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing 48
3-1 Introduction 48
3-2 Experiment 49
3-3 Results and Discussion 50
3-3-1 Effect of annealing ambient on crystallinity 50
3-3-2 Effect of annealing ambient on device performance 52
3-3-3 Raman analysis for poly-GeSn film 54
3-3-4 Bulk defect density of poly-GeSn film 55
3-3-5 SEM and AFM analysis for poly-GeSn film 56
3-3-6 Effect of different annealing ambient of mobility 58
3-4 Summary 59
3-5 References 60
Chapter 4 Poly-GeSn Junctionless P-TFTs Featuring Record High ION/IOFF Ratio Hole Mobility by Defect Engineering 73
4-1 Introduction 73
4-2 Experiment 75
4-3 Results and Discussion 76
4-3-1 Impact of plasma for device performance 76
4-3-2 Mechanism of device improvement 77
4-3-3 Reliability analysis 80
4-4 Summary 81
4-5 References 82
Chapter 5 Junctionless Poly-GeSn Ferroelectric TFTs with Improved Reliability by Interface Engineering for Neuromorphic Computing 92
5-1 Introduction 92
5-2 Experiment 95
5-3 Results and Discussion 97
5-3-1 Impact of channel material on ferroelectric performance 97
5-3-2 Physical Analysis 99
5-3-3 Plasma treatment effect on reliability of GeSn FE-TFTs 101
5-3-4 IL effect on reliability of plasma-treated GeSn FE-TFTs 102
5-3-5 Short term plasticity 105
5-3-6 Long term plasticity 108
5-3-7 Pattern recognition accuracy 110
5-3-8 Spike-timing-dependent plasticity 111
5-4 Summary 112
5-5 References 113
Chapter 6 Impact of GeSn Crystallinity on Reliability of Ferroelectric HfZrOx for Devices with Metal-Ferroelectric-Semiconductor Structure 137
6-1 Introduction 137
6-2 Experiment 139
6-3 Results and Discussion 140
6-3-1 Single crystal-GeSn fabrication by solid phase epitaxy 140
6-3-2 Metal-Ferroelectric-Semiconductor physical analysis 142
6-3-3 Ferroelectricity of HZO on single- or poly-GeSn substrate 143
6-3-4 Reliability of HZO on single- or poly-GeSn substrate 145
6-4 Summary 147
6-5 References 148
Chapter 7 Conclusions and Further Recommendations 161
7-1 Conclusions 161
7-2 Further Recommendations 164
Publication List 165
Journal 165
Conference 166  
Figure Captions
Chapter 1
Fig. 1.1 Schematic view of devices cross-section for 3D-IC applications with package level, wafer level and monolithic 3D-IC [1.14]. 16
Fig. 1.2 Schematic view of inversion-mode, accumulation-mode and junctionless FET [1.24]. 16
Fig. 1.3 Location of conduction path in different devices. Subthreshold conduction path in (a) inversion, (b)accumulation and (c)junctionless devices. Conduction channels above threshold in (d)inversion, (e)accumulation and (f)junctionless devices [1.24]. 17
Fig. 1.4 Schematic band structure of Ge and GeSn alloy. GeSn alloy is expected to become direct gap with Sn about 8% [1.6]. 17
Fig. 1.5 Relative different valley occupancy for Ge channel with nMOSFETs [1.6]. 18
Fig. 1.6 Relative different valley occupancy for GeSn (10% Sn) channel with nMOSFETs. Reduction of L-Γ energy gap in GeSn causes increased population of Γ valley. Alloying with Sn also increases L-Δ energy gap, inhibiting Δ valley occupancy at high fields [1.6]. 18
Fig. 1.7 Comparison of injection velocity (Vinj) in nMOSFETs with Ge and GeSn (10% Sn) as channel. Improvement in Vinj is expected with direct band gap GeSn (10% Sn) [1.6]. 19
Fig. 1.8 Effective masses, degeneracy (g) in direction along the channel (||), perpendicular to the channel (⊥) and along confinement axis (z) [1.6]. 19
Fig. 1.9 Due to the high scalability of FE-HfO2 the manufacturability of the gate stack is still given at the 28 nm node [1.37]. 20
Fig. 1.10 Qualitative illustration of two causes of why HfO2-based ferroelectric has longer retention (1) Edep/Ec in HfO2-based ferroelectric is less significant, leading to less sever initial retention loss due to depolarization field, and (2) trap concentration in HfO2 is much lower than its PZT and SBT counterparts, leading to much less retention loss due to trapping [1.38]. 20
Chapter 2
Fig. 2.1 Brief process flow, schematic of global and local SiO2 capping and final device structure of poly-GeSn JL P-TFTs. 38
Fig. 2.2 XRD patterns of poly-GeSn film annealed with different temperature and time in N2 ambient. 39
Fig. 2.3 ID-VG transfer curves for devices with poly-GeSn film of various thicknesses for VD biased at -0.05 V. 39
Fig. 2.4 Capacitance versus voltage for poly-GeSn MOS structure with various layer thickness measured at 100 kHz. 40
Fig. 2.5 XRD patterns of -GeSn film annealed at different temperatures for 30 sec with global SiO2 capping layer. 40
Fig. 2.6 XRD patterns of -GeSn film annealed at different temperatures for 30 sec without global SiO2 capping layer. 41
Fig. 2.7 Hole concentration of poly-GeSn film formed at different annealing temperatures for 30 sec with global SiO2 capping layer by Hall effect measurement. 41
Fig. 2.8 Hole concentration of poly-GeSn film formed at different annealing temperatures for 30 sec without global SiO2 capping layer by Hall effect measurement. 42
Fig. 2.9 ID-VG transfer curves for devices with poly-GeSn film formed with global SiO2 capping layer biased at VD of -0.05 V and -1 V. 42
Fig. 2.10 ID-VG transfer curves for devices with poly-GeSn film formed without global SiO2 capping layer biased at VD of -0.05 V and -1 V. 43
Fig. 2.11 ID-VG transfer curves for JL P-TFTs with and without local SiO2 capping layer on the S/D region. 43
Fig. 2.12 ID-VD output curves for JL P-TFTs with and without local SiO2 capping layer on the S/D region. 44
Fig. 2.13 AFM surface roughness for poly-GeSn film with and without SiO2 capping layer. 44
Fig. 2.14 3D image for poly-GeSn film with and without SiO2 capping layer. 45
Fig. 2.15 I-V curves between the contact metal (Ni) and S/D region with and without local SiO2 capping layer. 45
Fig. 2.16 Specific contact resistivity for poly-GeSn films with and without SiO2 capping layer. 46
Fig. 2.17 Field-effect hole mobility for JL P-TFTs with and without the capping layer on the S/D region. 46
Chapter 3
Fig. 3.1 Process flow and device structure of poly-GeSn JL P-TFT. 65
Fig. 3.2 XRD patterns for GeSn film with different annealing ambient at 500 oC for 30 sec. 65
Fig. 3.3 XRD enlarged pattern between 25o and 30o with different annealing ambient at 500 oC for 30 sec. 66
Fig. 3.4 ID-VG transfer curves for devices with different annealing ambient for VD biased at -0.05 V. 66
Fig. 3.5 ID-VD output curves for devices with different annealing ambient and biased at VG-Vt of -5 V. 67
Fig. 3.6 Capacitance versus voltage for devices with various annealing ambient measured at 1 and 100 kHz. 67
Fig. 3.7 Hole concentration for poly-GeSn film with different gas annealing. N2-annealed poly-GeSn film corresponds to a higher hole concentration. 68
Fig. 3.8 Raman spectra for GeSn film annealed by N2 and Ar gas. Spectrum for bulk Ge is also shown for reference. 68
Fig. 3.9 ln[ID/(VG–VFB)] versus 1/(VG–VFB)2 for Ar-, N2- and N2O-annealed devices for Nbulk extraction. 69
Fig. 3.10 The device structure and Sn precipitation analysis region (red frame) by EDS and SEM. 69
Fig. 3.11 EDS images of devices and no Sn precipitation are observed. 70
Fig. 3.12 AFM surface roughness for GeSn film annealed by various annealing gases. 70
Fig. 3.13 3D images for GeSn film as-deposited and annealed by various annealing gases. 71
Fig. 3.14 Field-effect hole mobility for devices with various annealing ambient. 71
Fig. 3.15 Hole mobility by Hall effect measurement for GeSn film annealed by various gases. 72
Chapter 4
Fig. 4.1 Process flow of high-performance poly-GeSn JL P-TFTs with defect engineering. Process conditions of each stage and the final structure of the devices are also presented. 85
Fig. 4.2 Bi-directional ID-VG transfer curves for Ar-gas-annealed devices with additional plasma treatments. NH3 plasma shows the best ION/IOFF ratio and drive current. 85
Fig. 4.3 ID-VG hysteresis for 10 devices with various plasma treatments. 86
Fig. 4.4 Gate leakage for devices with various plasma treatments. 86
Fig. 4.5 Bi-directional ID-VD output curves for devices with different plasma treatment under the same overdrive voltage. NH3 plasma outperforms other plasma treatments. 87
Fig. 4.6 Capacitance for devices with various plasma treatments. Tiny frequency dispersion in the depletion region for NH3 and N2 plasma implies good interfacial quality. 87
Fig. 4.7 Field-effect hole mobility vs. E-field for devices with various plasma treatments. A record high peak mobility of 162.2 cm2/Vs is obtained by NH3 plasma. 88
Fig. 4.8 XRD patterns for GeSn film annealed by Ar gas with additional plasma treatment. 88
Fig. 4.9 ln[ID/(VG–VFB)] vs. 1/(VG–VFB)2 for Ar-gas annealed devices with additional plasma treatments for Nbulk extraction. 89
Fig. 4.10 Gate current for Ar-gas-annealed devices with additional plasma treatments. Data for devices with only Ar annealing is also shown for comparison. 89
Fig. 4.11 SILC as a function of stress time under the gate stress field of -10 MV/cm for devices with different treatments. 90
Fig. 4.12 Vt shift as a function of stress time under the gate stress field of -10 MV/cm for devices with different treatments. Additional plasma treatment greatly suppresses Vt shift. 90
Chapter 5
Fig. 5.1 Process flow of 2-stage investigation on high-performance poly-Ge and poly-GeSn junctionless TFT devices based on Fe-HZO. Process condition of each stage and the final structure of the devices are also presented. 121
Fig. 5.2 XRD patterns for Fe-HZO with poly-Ge and poly-GeSn channel. 122
Fig. 5.3 I-V characteristics for Fe-TFTs with poly-Ge and poly-GeSn channel. 122
Fig. 5.4 P-V curves for Fe-TFTs with poly-Ge and poly-GeSn channel. 123
Fig. 5.5 Endurance performance for Fe-TFTs with poly-Ge and poly-GeSn channel. 123
Fig. 5.6 SS and OS retention performance at 85 oC for Fe-TFTs with poly-Ge and poly-GeSn channel. 124
Fig. 5.7 Cross-sectional TEM image of JL poly-GeSn Fe-TFTs. 124
Fig. 5.8 Top view SEM image of poly-GeSn channel and Ni S/D region. The inset shows the EDS elemental mapping of Sn for poly-GeSn channel. 125
Fig. 5.9 AFM surface morphology for poly-GeSn film. 125
Fig. 5.10 PFM image of HZO with and without GeSn channel capping. 126
Fig. 5.11 Impact of NH3 plasma treatment of poly-GeSn channel on P-V characteristics for Fe-TFTs. 126
Fig. 5.12 Impact of NH3 plasma treatment of poly-GeSn channel on gate leakage I-V curves for Fe-TFTs. 127
Fig. 5.13 Impact of NH3 plasma treatment of poly-GeSn channel on endurance performance and for Fe-TFTs. 127
Fig. 5.14 Impact of NH3 plasma treatment of poly-GeSn channel on SS and OS retention at 85 oC for Fe-TFTs. 128
Fig. 5.15 Dependence of various IL on gate leakage I-V curves for Fe-TFTs with plasma-treated poly-GeSn channel. 128
Fig. 5.16 Dependence of various IL on XRD patterns for Fe-TFTs with plasma-treated poly-GeSn channel. 129
Fig. 5.17 Dependence of various IL on P-V characteristics for Fe-TFTs with plasma-treated poly-GeSn channel. 129
Fig. 5.18 Dependence of various IL on endurance performance for Fe-TFTs with plasma-treated poly-GeSn channel. 130
Fig. 5.19 Dependence of various IL on SS and OS retention at 85 oC for Fe-TFTs with plasma-treated poly-GeSn channel. 130
Fig. 5.20 Dependence of various IL on ID-VG transfer curves for Fe-TFTs with plasma-treated poly-GeSn channel. 131
Fig. 5.21 PPD behaviors of short-term plasticity imitated on poly-GeSn Fe-TFTs. Waveform of the paired pulse applied at gate terminal and corresponding waveform of the drain current. 131
Fig. 5.22 PPD behaviors of short-term plasticity imitated on poly-GeSn Fe-TFTs. Dipole switching characteristic with different pulse width. 132
Fig. 5.23 PPD behaviors of short-term plasticity imitated on poly-GeSn Fe-TFTs. Dependence of pulse width on PPD current index. 132
Fig. 5.24 Two training pulse schemes (Scheme A: pulse width modulation, Scheme B: pulse amplitude modulation) for potentiation/depression. 133
Fig. 5.25 Channel conductance (G) as a function of pulse number for Scheme A (LTP) for plasma-treated GeSn Fe-TFTs with Ta2O5 IL. 133
Fig. 5.26 Channel conductance (G) as a function of pulse number for Scheme A (LTD) for plasma-treated GeSn Fe-TFTs with Ta2O5 IL. 134
Fig. 5.27 Channel conductance (G) as a function of pulse number for Scheme B (LTD) for plasma-treated GeSn Fe-TFTs with Ta2O5 IL. 134
Fig. 5.28 Channel conductance (G) as a function of pulse number for Scheme B (LTD) for plasma-treated GeSn Fe-TFTs with Ta2O5 IL. 135
Fig. 5.29 Evolution of pattern recognition accuracy with training epochs for scheme A and scheme B on MNIST dataset. 135
Fig. 5.30 Waveform of pulse at pre-synaptic neuron and post-synaptic neuron. Voltage drop across pre-synaptic and post-synaptic neuron is also shown. 136
Fig. 5.31 STDP behaviors imitated on poly-GeSn Fe-TFTs by showing conductance change (ΔG) as a function of interval time (Δt). 136
Chapter 6
Fig. 6.1 Process flow of M-F-S devices on poly-crystal or single-crystal GeSn substrate by solid phase epitaxy and capping layer effect. 152
Fig. 6.2 XRD patterns and for single-crystalline GeSn film with and without SiO2 capping layer. 152
Fig. 6.3 AFM surface roughness for single-crystalline GeSn film with and without SiO2 capping layer. 153
Fig. 6.4 TEM image for single-crystalline GeSn film after removing SiO2 capping layer 153
Fig. 6.5 TEM and FFT image for the whole semiconductor materials including Si substrate, SiGeSn interface layer and single-crystalline GeSn film. 154
Fig. 6.6 EDS image of single-crystalline GeSn film (Sn of 5.1%) on Si (111) substrate after removing SiO2 capping layer. 154
Fig. 6.7 XRD patterns for HZO on single- or poly-crystalline GeSn film. 155
Fig. 6.8 TEM image of HZO on single-crystalline GeSn film 155
Fig. 6.9 TEM image of HZO on poly-crystalline GeSn film 156
Fig. 6.10 I-E hysteresis loops of HZO on single- or poly-crystalline GeSn films. 156
Fig. 6.11 P-E hysteresis loops of HZO on single- or poly-crystalline GeSn films. 157
Fig. 6.12 Dipole switched speed of HZO on poly-crystalline GeSn films at different electric field. 157
Fig. 6.13 Dipole switched speed of HZO on single-crystalline GeSn films at different electric field. 158
Fig. 6.14 AFM surface roughness for poly- and single-crystalline GeSn film with SiO2 capping layer. 158
Fig. 6.15 Endurance of HZO on poly- and single-crystalline GeSn films at 3.3 MV/cm for 106 cycles. 159
Fig. 6.16 SS retention of HZO on poly- and single-crystalline GeSn films for 104 sec. 159
Fig. 6.17 OS retention of HZO on poly- and single-crystalline GeSn films for 104 sec. 160
Fig. 6.18 OS retention of positive coercive voltage shift for 104 sec. 160





 
Table Lists
Chapter 2
Table I. Comparison of ION/IOFF, peak mobility and several parameters for poly-Ge and poly-GeSn P-TFTs devices. 47
Chapter 3
Table I. Comparison of major device parameters for group IV P-TFTs. 72
Chapter 4
Table I. Comparison of ION/IOFF, peak mobility and several parameters for poly-Ge and poly-GeSn P-TFTs devices. 91

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