鰭式電晶體相較於傳統單閘極平面式電晶體有更好的閘極控制能力，驅動電流的提升、降低漏電流、並展現出接近理想值的次臨界擺幅(SS) 、更小的汲極引致能障下降(DIBL)，甚至是元件更佳可靠度的表現。
此篇論文的研究中，我們是第一個提出比較次二十奈米累積型與無接面N型鰭式電晶體和傳統的反轉N型鰭式電晶體之研究。首先，我們利用改變通道參雜，並採用合適的金屬閘極功函數製程，對電晶體做電性上的分析與討論。此元件成功展現出極佳的電特性，像是SS達到接近理想值的64mV/dec以及高於1×108開關特性，主要是基於元件通道做得夠薄，使的閘極擁有更好的控制能力。另外此元件對於克服短通道效應的控制上展現出極佳的能力，其DIBL值為20mV/V，更小的元件變易量以提升元件的製造良率，甚至是更好的電晶體可靠度等等。
在此篇研究中首先是專注在元件製程以及基礎元件特性分析，接下來為了測試此元件在應用面的廣度，我們會對此元件進行變易量及萃取元件的電子遷移率最後可靠度分析，在高壓下熱載子對元件VT產生電性上劣化的反應。

對於元件的電性分析上，此研究利用傳統電晶體當其對照組，去比較無接面電晶體與傳統有PN接面的電晶體之各種電性分析反應，並搭配TCAD模擬軟體3D結構的建模，去模擬其能帶在元件中的分布，由模擬的結果，可知此無接面電晶體在未來有機會應用於更先進元件且耐高壓領域。除此之外，由模擬中可知，此無接面電晶體因為沒有PN接面，在通道關閉的狀態時，其等效閘極長度是長於傳統電晶體的，所以元件對於汲極引致能障下降 (DIBL)的影響是較小的。
由於採用P型的金屬公函數閘極，載子在無接面電晶體傳輸的路徑，會因為閘極與參雜的矽通道的公函數差，使得通道完全空乏，並將載子推到通道中間，因此受到高電場表面散射的影響較小，有助於提升元件的電子遷移率，並提升ION。
在熱載子對元件產生的劣化反應分析中，我們針對比較Inversion-mode、Accumulation-mode以及Junctionless-mode FinFET進行分析，由實驗中發現，Junctionless-mode比起Inversion-mode在熱載子對元件產生的劣化反應分析中擁有較佳的可靠度，因為元件Junctionless-mode FinFET 水平方向的能帶梯度較小，所以無接面電晶體在元件中的等效電場比起傳統PN接面電晶體來的低，鑒於以上的論述，Junctionless-mode FinFET擁有較低的熱載子對元件產生的劣化行為。
在此篇研究中，我們首先提出次二十奈米之Accumulation-mode以及Junctionless-mode N型鰭式電晶體。其展現出了極佳的電特性、擁有較小的變異度，相當好的耐壓能力以及理想的抗熱載子對元件產生的劣化反應。

The FinFET structure transistor has better gate controllability comparing with traditional planar transistor, which can increase the drive current, reduce the leakage current. Subthreshold Swing (SS) is close to the ideal value, and the smaller Drain Induced Barrier Lowing (DIBL), and even better reliability performance.
In this thesis, we are the first time to propose the sub-20 nm accumulation-mode (AC) and junctionless-mode (JL) N-type FinFET transistors. First, we change the channel doping species, and adopt appropriate workfunction metal gate process. Further do the electrical analysis and discussion comparing with the conventional inversion-mode (IM) N-type FinFET (STD). Our experimental devices are successfully fabricated and exhibits excellent electrical property, such as SS is measured as 64mV/dec close to ideal value and higher than 1×108 switching transfer characteristic. Mainly base on the Fin channel is thin and narrow enough to have good gate controllability. Moreover, accumulation-mode (AC) and junctionless-mode (JL) structures present excellent performance to overcome the short channel effect with DIBL value at 20 mV/V. Smaller electrical property variation within wafer may improves the yield for device manufacturing, and even better reliability, etc.
In this study, we first focus on the device electrical analysis among the accumulation-mode (AC), junctionless-mode (JL) and inversion-mode (IM) N-type FinFET (STD). In order to test the breadth of the application, we further analyze the 10 sites variability of the devices and the extraction mobility analysis for the experiment. Stress the devices shows the reaction of the device VT deterioration under channel hot carrier (CHC) with 1500 sec.
By 3D TCAD simulation software, simulates the distribution of its energy band diagram in any conditions. In addition, it also can be learned from the simulation, junctionless-mode (JL) structure owing to has no physical PN junction, at off state, the equivalent gate length is longer than the conventional transistor, so the component for the effect of DIBL is smaller.
Adopting the P-type workfunction metal gate, the carrier transmission path in the junctionless-mode (JL) transistor is formed as the body current. Consequently, junctionless-mode (JL) transistor effect by the impact of surface scattering is getting smaller, helps to enhance the electronic mobility and increase the drive current ION.
In the analysis of the degradation reaction of the thermal carrier to the component, we analyze the comparison of Inversion-mode, Accumulation-mode and Junctionless-mode FinFET. It is found that Junctionless-mode (JL) FinFET has a better reliability in the degradation reaction analysis, since the energy band gradient of the element Junctionless-mode FinFET in the horizontal direction is smaller, the equivalent electric field of the transistor in the element is smaller than that of the conventional PN junction transistor. Conclude above discussion, junctionless-mode (JL) FinFET has a lower thermal carrier on the components of the degradation behavior.
In this study, we first propose the sub 20 nm accumulation-mode (AC) and junctionless-mode (JL) N-type FinFET transistors. It exhibit excellent electrical characteristics, with a small variability, and very good reliability on the channel hot carrier (CHC) stress for the device degradation, also the good characteristics for advanced low power consumption applications and three-dimensional (3-D) stacked ICs applications.

Contents
中文摘要…… i
Abstract……… iii
Acknowledge… v
Contents…….. vi
Table Captions vii
Figure Captions vii
Chapter 1……. - 1 -
Introduction…. - 1 -
1-1 Challenge of Scaling Down the Device - 1 -
1-2 Design of FinFET Structure - 4 -
1-3 The Same Doping Type of Gate and S/D - 5 -
1-4 Adoption of Suitable Workfunction Metal Gate - 6 -
1-5 Motivation - 7 -
1-6 Thesis Organization - 8 -
Chapter 2……. - 9 -
Motivation of Accumulation and Junctionless Device - 9 -
2-1 Basic Design Guideline of MOSFET Transistor - 9 -
2-2 High Immunity Device to Short Channel Effect (SCE) - 15 -
2-3 Scattering Effect on Device Mobility - 18 -
2-4 Superiority of No Physical PN Junction Device - 20 -
Chapter 3……. - 22 -
Device Fabrication and Device Simulation - 22 -
3-1 FinFET Fabrication Process - 22 -
3-2 Experiment Management - 25 -
3-3 Device Electrical Property Measurement - 27 -
3-4 Device Simulation - 29 -







Chapter 4……. - 32 -
Implanting N-type Channel Implant w/ N-type MG of FinFET - 32 -
4-1 Device Electrical Analysis - 32 -
4-2 Variation Results and Discussions - 36 -
4-3 Mobility Characteristic Effect on Device Performance - 40 -
4-4 Reliability Study on Device Performance - 42 -
4-5 Conclusion - 44 -
Chapter 5……. - 45 -
Implanting N-type Channel Implant w/ P-type MG of FinFET - 45 -
5-1 Device Electrical Analysis - 45 -
5-2 Variation Results and Discussions - 50 -
5-3 Mobility Characteristic Effect on Device Performance - 55 -
5-4 Reliability Study on Device Performance - 58 -
5-5 Conclusion - 61 -
Chapter 6……. - 62 -
Conclusion….. - 62 -
Reference…… - 64 -


Table Captions

Table 3-1 Channel implant P31 with five different concentration conditions under twotypesof workfunction metal gate (N/P MG) to implement the AC-mode and JL-mode FinFET devices. (Split table) - 26 -




Figure Captions
Figure 1- 1 2015 ITRS roadmap v.2. - 2 -
Figure 1- 2 Equivalent length between inversion-mode (IM) and junctionless-mode (JL) devices. - 2 -
Figure 1- 3 Advantage process and structures of devices in every generation nodes. ……………………………………………………………………..- 3 -
Figure 1- 4 TSMC 16nm transfer ID–VG characteristics of FinFET. - 4 -
Figure 1- 5 The junctionless-mode (JL) device with P-type metal gate. - 6 -

Figure 2- 1 Drain current (log scale) as a function of gate voltage (a) inversion mode device. (b) accumulation-mode device (c) a heavily-doped junctionless transistor [2-1]………………………………………- 10 -
Figure 2- 2 Electron concentration profile above threshold voltage [2-1]. - 11 -
Figure 2- 3 Electron concentration plots in an n-type junctionless transistor for VDS = 50 mV. (a) VGVTH; (d) VG = VFB>> VTH [2-1] …………………………………………- 12 -
Figure 2- 4 Location of conduction path in the different devices, for below threshold voltage and above threshold [2-1]. - 14 -
Figure 2- 5 (a) Bird eye’s view of a JNTs and IM nanowire MOSFETsand (b) doping profile in the longitudinal direction in JNTs and IM devices. [2-2]. - 16 -
Figure 2- 6 Illustration of effective channel length in an inversion-mode (IM) device (a) and a junctionless (JL) transistor (b) [2-1]. - 16 -
Figure 2- 7 Illustration of the effective gate length variation from the off-state to theon-state (right) in a JNT using the plot of charge carrier concentration (left). The dark areas are neutral (i.e., not depleted).The depleted region is transparent [2-2]. - 17 -
Figure 2- 8 Decrease of source-channel barrier due to increasing of drain voltage in (a) JL devices and (b) IM devices [2-2]. - 17 -
Figure 2- 9 An electron can be scattered by an acceptor ion (a) and a donor ion (b) in a strikingly similar manner, even though the ions carry opposite types of charge. - 18 -
Figure 2- 10 Transfer Id-Vg characteristics of JL-GAA and JL-Planar TFTs. Inset: DIBL characteristics of both devices [2-5]. - 21 -
Figure 2- 11 Typical transfer characteristics of all splits of devices with channel length of 0.4μm [2-6]………………………………………... - 21 -



Figure 3- 1 Fin mandrel patterning and STI formation. - 23 -
Figure 3- 2 STI recess and Gate oxide formation. - 23 -
Figure 3- 3 Dummy gate definition and Spacer formation. - 24 -
Figure 3- 4 S/D epitaxial growth and Gate last high-k MG. - 24 -
Figure 3- 5 Device structure and parameters of simulated IM and AC FinFET device with wine-shaped thin fin. - 30 -
Figure 3- 6 Experimental and simulated Id–Vg curves for inversion-mode (IM) FinFET. The inset shows simulated devices with Lg=16nm. - 30 -
Figure 3- 7 Experimental and simulated Id–Vg curves for accumulation-mode (AC) FinFET. The inset shows simulated devices with Lg=16nm. - 31 -
Figure 3- 8 Experimental and simulated Id–Vg curves for junctionless-mode (JL) FinFET. The inset shows simulated devices with Lg=16nm. - 31 -

Figure 4- 1 The transfer ID–VG characteristics of inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET with the same workfunction n-type metal gate at VD = 0.8 V. - 33 -
Figure 4- 2 The value of VT and SS with inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET. - 34 -
Figure 4- 3 The transfer ID–VD curves of inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET with the same workfunction n-type metal gate at Vov = 0V, 0.5V, 1V and 1.5V. - 35 -
Figure 4- 4 The value of VT and Ion with inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET. - 35 -
Figure 4- 5 10 sites VT variation of nFinFET device. - 36 -
Figure 4- 6 10 sites SS variation of nFinFET device. - 37 -
Figure 4- 7 10 sites Ion variation of nFinFET device. - 38 -
Figure 4- 8 10 sites Ioff variation of nFinFET device. - 38 -
Figure 4- 9 10 sites DIBL variation of nFinFET device. - 39 -
Figure 4- 10 Comparison mobility of inversion-mode (IM) and accumulation-mode (AC) nFinFET device. - 41 -
Figure 4- 11 Comparison of lateral field and impact ionization between AM and JL pMuGFETs [4-6]. …………………………………………………………………..- 42 -
Figure 4- 12 Comparison of VT shift degradation after CHC stress between IM and AC nFinFETs with n-type MG after 1500 sec stress at VOV = 0.8V, Vd = 2V. - 43 -

Figure 5- 1 Band chart shows n-type channel and with the p-type MG - 45 -
Figure 5- 2 Demonstrates the comparison of n-channel junctionless-mode (JL) structure device between n-type metal gate (nMG) and p-type metal gate (pMG). - 46 -
Figure 5- 3 The transfer ID–VG characteristics of inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET with the same workfunction p-type metal gate at VD = 0.8 V. - 48 -
Figure 5- 4 The transfer ID–VD curves of inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET with the same workfunction p-type metal gate at Vov = 0V, 0.5V, 1V and 1.5V. - 49 -
Figure 5- 5 The value of VT and Ion for inversion-mode (IM), accumulation-mode (AC), and junctionless-mode (JL) nFinFET. - 50 -
Figure 5- 6 10 sites VT variation of nFinFET device. - 51 -
Figure 5- 7 10 sites SS variation of nFinFET device. - 52 -
Figure 5- 8 10 sites Ion variation of nFinFET device. - 53 -
Figure 5- 9 10 sites Ioff variation of nFinFET device. - 53 -
Figure 5- 10 10 sites DIBL variation of nFinFET device. - 54 -
Figure 5- 11 Comparison mobility of inversion-mode (IM) and accumulation-mode (AC) nFinFET device. - 56 -
Figure 5- 12 Comparison of VT shift degradation after CHC stress between IM、… …………………………………………………………………..- 59 -
Figure 5- 13 Demonstrates the situation of channel hot carrier (CHC) stress at VOV = 0.8V, and Vd = 2V. …………………………………………………………………..- 60 -
Figure 5- 14 Explain the horizontal direction of the electric field among IM, AC, and JL structure devices. - 60 -

Reference
Chapter 1

[1-1] D. Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, 2000.
[1-2] S. Y. Wu et al., “A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications,” Tech. Dig. - Int. Electron Devices Meet. IEDM, pp. 224–227, 2013.
[1-3] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
[1-4] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[1-5] T. Matsukawa et al., “Suppressed Variability of Current-onset Voltage of FinFETs by Improvement of Work Function Uniformity of Metal Gates,” 2013 Int. Symp. VLSI Technol. Syst. Appl. VLSI-TSA 2013, vol. 2197, no. 2011, pp. 2011–2012, 2013.H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., pp. 131–132, 2010.
[1-6] T. Matsukawa et al., “Fluctuation in Drain Induced Barrier Lowering (DIBL) for FinFETs Caused by Granular Work Function Variation of Metal Gates,” Proc. Tech. Progr. - 2014 Int. Symp. VLSI Technol. Syst. Appl. VLSI-TSA 2014, vol. 3055, no. 2009, pp. 9–10, 2014.
 

Chapter 2

[2-1] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
[2-2] P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J. Colinge, “Influence of channel material properties on performance of nanowire transistors,” J. Appl. Phys., vol. 111, no. 12, pp. 124509-1–124509-8, Jun. 2012.
[2-3] Chenmming Hu , Modern Semiconductor Devices for IC, 2010.
[2-4] Lun-Chun Chen, Mu-Shih Yeh, and Yung-Chun Wu, “The physical analysis on electrical junction of junctionless FET,” AIP Advances 7, 025301 (2017)
[2-5] L. Horng-Chih, I. L. Cheng, L. Zer-Ming, S. Bo-Shiuan, and H. Tiao-Yuan, "Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness," Electron Devices, IEEE Transactions on, vol. 60, pp. 1142-1148, 2013.
[2-6] C. Hung-Bin, C. Chun-Yen, L. Nan-Heng, W. Jia-Jiun, H. Ming-Hung, C. Ya-Chi, et al., "Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel," Electron Device Letters, IEEE, vol. 34, pp. 897-899, 2013.
 

Chapter 3

[3-1] S. Gupta, V. Moroz, L. Smith, Q. Lu, and K. C. Saraswat, “A Group IV Solution for 7nm FinFET CMOS : Stress Engineering Using Si , Ge and Sn,” IEDM,2013.
[3-2] S.-P. Sun, S.-L. Wang, C.-H. Lin, N.-K. Chen, and C. H. Wann, “Method of making a FINFET device, ” 2014.
[3-3] Chi-Woo, J.P. Colinge, “Junctionless multigate field-effect transistor”APL,2009.
[3-4] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.


Chapter 4

[4-1] Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge,“Junctionless multigate field-effect transistor,” APL,2009.
[4-2] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
[4-3] Chenmming Hu , Modern Semiconductor Devices for IC, 2010.
[4-4] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[4-5] Jong Tae Park, Jin Young Kim and Jean Pierre Colinge, “Negative-bias-temperature-instability and hot carrier effects in nanowirejunctionless p-channel multigate transistors”, APL, vol. 100, pp. 083505-1 – 083505-3, 2012.
 

Chapter 5

[5-1] Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge,“Junctionless multigate field-effect transistor,” APL,2009.
[5-2] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
[5-3] Chenmming Hu , Modern Semiconductor Devices for IC, 2010.
[5-4] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[5-5] Jong Tae Park, Jin Young Kim and Jean Pierre Colinge, “Negative-bias-temperature-instability and hot carrier effects in nanowirejunctionless p-channel multigate transistors”, APL, vol. 100, pp. 083505-1 – 083505-3, 2012.