|
[1] C. H. Fu et al., “Enhanced Hole Mobility and Low Tinv for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel,” IEEE Electron Device Letters, vol. 33, no. 2. pp. 188–190, 2012. [2] S. Maikap, M. H. Lee, S. T. Chang, and C.W.Liu, “Characteristics of strained-germanium p- and n-channel field effect transistors on a Si (1 1 1) substrate,” Semicond. Sci. Technol., vol. 22, no. 4, pp. 342–347, 2007. [3] W. P. Bai, N. Lu, and D. L. Kwong, “Si interlayer passivation on germanium MOS capacitors with high-k dielectric and metal gate,” IEEE Electron Device Letters, vol. 26, no. 6. pp. 378–380, 2005. [4] J. H. Stathis and D. J. DiMaria, “Reliability projection for ultra-thin oxides at low voltage,” International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), no. 3. pp. 167–170, 1998. [5] H. S. Momose et al., “Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET’s: Uniformity, reliability, and dopant penetration of the gate oxide,” IEEE Transactions on Electron Devices, vol. 45, no. 3. pp. 691–700, 1998. [6] J. Robertson, “Electronic behavior of high K oxides,” Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004., vol. 1. pp. 384–387, 2004. [7] L. LUCCI et al., “Quantitative Assesment of mobility degradation by Remote Coulomb Scattering in Ultra-thin oxide MOSFETs: measurement and simulations,” Proceedings of International Electron Devices Meeting (IEDM), 2003. pp. 463–466, 2003. [8] H. Ota et al., “Intrinsic origin of electron mobility reduction in high-k MOSFETs - From remote phonon to bottom interface dipole scattering,” Technical Digest - International Electron Devices Meeting, IEDM. pp. 65–68, 2007. [9] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, “High-mobility Ge pMOSFET With 1-nm EOT Al2O3 GeOx Ge gate stack fabricated by plasma post oxidation,” IEEE Transactions on Electron Devices, vol. 59, no. 2. pp. 335–341, 2012. [10] K. Kita et al., “Comprehensive study of GeO2 oxidation, GeO desorption and GeO2-metal interaction: Understanding of Ge processing kinetics for perfect interface control,” Technical Digest - International Electron Devices Meeting, IEDM. pp. 1–4, 2009. [11] Y. Fukuda, Y. Yazaki, Y. Otani, T. Sato, H. Toyota, and T. Ono, “Low-temperature formation of high-quality GeO2 interlayer for high-K gate dielectrics/Ge by electron-cyclotron-resonance plasma techniques,” IEEE Transactions on Electron Devices, vol. 57, no. 1. pp. 282–287, 2010. [12] C. H. Lee et al., “Ge MOSFETs performance: Impact of Ge interface passivation,” Technical Digest - International Electron Devices Meeting, IEDM. p. 18.1.1-18.1.4, 2010. [13] T. Takahashi, T. Nishimura, L. Chen, S. Sakata, K. Kita, and A. Toriumi, “Proof of Ge-interfacing concepts for metal/high-k/Ge CMOS - Ge-intimate material selection and interface conscious process flow,” Technical Digest - International Electron Devices Meeting, IEDM. pp. 697–700, 2007. [14] C. H. Lee, T. Nishimura, K. Nagashio, K. Kita, and A. Toriumi, “High-electron-mobility Ge/GeO2 n-MOSFETs with two-step oxidation,” IEEE Transactions on Electron Devices, vol. 58, no. 5. pp. 1295–1301, 2011. [15] S. H. Yi, K. S. Chang-Liao, T.Wu, C. Hsu, and J. Huang, “High Performance Ge pMOSFETs With HfO2 /Hf-Cap/GeOx Gate Stack and Suitable Post Metal Annealing Treatments,” IEEE Electron Device Letters, vol. 38, no. 5. pp. 544–547, 2017. [16] W. J. Zhu and T. P.Ma, “Temperature Dependence of Channel Mobility in HfO2-Gated NMOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2. pp. 89–91, 2004. [17] Y. X. Zheng et al., “In situ process control of trilayer gate-stacks on p-germanium with 0.85-nm EOT,” IEEE Electron Device Lett., vol. 36, no. 9, pp. 881–883, 2015. [18] H. Y. Yu et al., “High quality single-crystal germanium-on-insulator on bulk Si substrates based on multistep lateral over-growth with hydrogen annealing,” Appl. Phys. Lett., vol. 97, no. 6, pp. 95–98, 2010. [19] E. Cartier, J. H. Stathis, and D. A. Buchanan, “Passivation and depassivation of silicon dangling bonds at the Si/SiO2 interface by atomic hydrogen,” Appl. Phys. Lett., vol. 63, no. 11, pp. 1510–1512, 1993. [20] X. Garros et al., “Guidelines to improve mobility performances and BTI reliability of advanced High-K/Metal gate stacks,” Digest of Technical Papers - Symposium on VLSI Technology. pp. 68–69, 2008. [21] H. Watanabe, K. Kutsuki, I. Hideshima, G. Okamoto, T. Hosoi, and T. Shimura, “High-quality GeON gate dielectrics formed by plasma nitridation of ultrathin thermal oxides on Ge(100),” ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. pp. 867–870, 2010. [22] Y. J. Lee et al., “Low-temperature microwave annealing for MOSFETs with High-k/metal gate stacks,” IEEE Electron Device Lett., vol. 34, no. 10, pp. 1286–1288, 2013. [23] L. Lin, K. Xiong, and J. Robertson, “Atomic structure, electronic structure, and band offsets at Ge:GeO:GeO2 interfaces,” Appl. Phys. Lett., vol. 97, no. 24, p. 242902, 2010. [24] D. Kuzum et al., “Ge-interface engineering with ozone oxidation for low interface-state density,” IEEE Electron Device Lett., vol. 29, no. 4, pp. 328–330, 2008. [25] Y. Nakakita, R. Nakakne, T. Sasada, M. Takenaka, and S. Takagi, “Interface-controlled self-align source/drain Ge p-channel metal-oxide-semiconductor field-effect transistors fabricated using thermally oxidized Geo2 interfacial layers,” Jpn. J. Appl. Phys., vol. 50, no. 1, 2011. [26] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “Thermal decomposition pathway of Ge and Si oxides observation.pdf,” vol. 369, pp. 289–292, 2000. [27] S. Maikap et al., “Effects of interfacial NH3/N2O-plasma treatment on the structural and electrical properties of ultra-thin HfO2 gate dielectrics on p-Si substrates,” Solid. State. Electron., vol. 49, no. 4, pp. 524–528, 2005. [28] C. S. Lai, W. C. Wu, K. M. Fan, J. C. Wang, and S. J. Lin, “Effects of post CF4 plasma treatment on the HfO2 thin film,” Japanese J. Appl. Physics, Part 1 Regul. Pap. Short Notes Rev. Pap., vol. 44, no. 4 B, pp. 2307–2310, 2005. [29] C. C. Li et al., “Low inversion equivalent oxide thickness and enhanced mobility in MOSFETs with chlorine plasma interface engineering,” Solid. State. Electron., vol. 101, pp. 33–37, 2014.
|