本論文主要是研究應用於電晶體源極與汲極之金屬半導體化合物的接觸特性。隨著元件尺寸微縮至7奈米技術節點以後，源極與汲極的接觸電阻率逐漸主導整體電晶體源極與汲極的電阻，許多團隊已朝如何降低接觸電阻率進行多方面的研究。在第二章節中，平均自由路徑較小的鈷展現優異的線電阻率且滿足Barrier-less而取代了金屬0層(M0)中的W-plug，故已有文獻提出從金屬Plug至源/汲極接觸以鈷材料整合之Co-plug/CoTi/CoSix結構的概念，這說明以鈷作為未來接觸結構的材料將備受重視。在本研究中，利用原子層沉積系統或濺鍍系統沉積金屬鈷於n型矽(n-Si)薄膜上，比較不同沉積系統沉積金屬鈷搭配快速熱退火所形成矽化鈷的接觸電阻率，觀察出利用原子層沉積系統所形成矽化鈷展現低於利用濺鍍系統所形成矽化鈷的接觸電阻率，原因為利用原子層沉積系統沉積金屬鈷比濺鍍系統沉積金屬鈷所形成矽化鈷與矽的介面粗糙度較為平坦，故而減少介面處的散射效應使得接觸電阻率有所改善。藉此應證原子層沉積系統值得取代濺鍍系統應用到新世代元件的源極/汲極。
為了突破矽的材料極限，導入高載子遷移率且有潛力與矽積體電路整合的鍺、錫化鍺材料於電晶體的源極與汲極已備受矚目。然而，金屬於鍺材料上具有相當嚴重的費米能階釘札效應(Fermi-level Pinning Effect)必須克服才能改善接觸電阻率，現今多數論文已朝金屬鍺化物的方向來緩解此效應並期許透過改善薄膜的結晶品質、均勻性與介面粗糙度來近一步降低接觸電阻率。本論文第三至四章主要建立在鍺與錫化鍺材料上開發出具有優異接觸電阻率的金屬接觸技術。在第三章節中，有鑑於已知利用原子層沉積系統沉積鈷有益於改善接觸電阻率下，進一步搭配雷射熱退火或快速熱退火與n型鍺(n-Ge)形成鍺化鈷，觀察出雷射熱退火下的鍺化鈷不但與鍺的介面品質更優異且達到原子級平坦的效果，並展現單晶的CoGe2薄膜。在接觸電阻率特性上展現優異於快速熱退火所形成的鍺化鈷，近一步降低接觸電阻率。在第四章節中，利用低功函數的金屬材料鐿(Yb)沉積於n型錫化鍺(n-GeSn)並搭配二氧化矽、非晶錫化鍺不同的覆蓋層，經過快速熱退火形成Yb Stanogermanide，兩種樣品皆展現緩解費米能階釘札的效果，其中非晶錫化鍺覆蓋層形成的Yb Stanogermanide具有更為均勻的薄膜品質、較為平坦的介面粗糙度、較小的電子蕭特基能障，而表現更優異的接觸電阻率。
最後，在第五章節中，主要探討如何改善穿隧式電晶體的雙極性效應(Ambipolar Effect)來提升元件的性能，若要使穿隧式電晶體整合於現今成熟CMOS技術，改善其開啟電流與雙極性電流(Ambipolar Current)而達到次臨界擺幅(Subthreshold Swing，SS )能小於60 mV/dec是其近年來受到矚目的焦點。本實驗以TCAD模擬軟體之結果呈現，探討傳統穿隧式電晶體的汲極工程，以改善長久為之詬病的雙極性電流為目的。本模擬採用SOI-FinFET結構進行研究，提出以矽化物金屬汲極取代傳統摻雜式矽汲極之新穎金屬汲極穿隧式電晶體(P-I-M TFET)，其具有優異抑制雙極性電流與更低關閉電流的效果。這是由於改善元件在汲極端的帶對帶穿隧率(Band-to-Band Tunneling Rate)與蕭克利-里德-霍爾復合率(Shockley-Read-Hall Recombination Rate)。其中汲極的金屬功函數為4.25 eV時表現出最佳性能，這意味著存在最佳選擇汲極的金屬功函數的設計指標。儘管如此，仍然必須評估技術窗口以容忍金屬功函數的變化。研究結果指出金屬汲極穿隧式電晶體的允許金屬功函數變化（製程窗口）是0.15 eV使漏電流優於傳統穿隧式電晶體。總結以上，金屬汲極穿隧式電晶體的金屬汲極工程將有潛力取代摻雜式矽汲極應用於未來的綠能元件。

This thesis focuses on studying the metal-semiconductor contact characteristics for advanced source and drain of the field-effect transistor. As device dimensions shrink beyond the 7nm technology node, the contact resistivity of the source and drain gradually dominates the source and drain resistance of the overall transistor. To resolve this issue, most studies have conducted various research on how to reduce contact resistivity. Chapter 2 of this thesis will cover this topic. With a shorter mean free path, Cobalt demonstrates excellent line resistivity and satisfies the barrier-less requirement, replacing the W-plug in metal 0 layer (M0). Therefore, the literature has proposed a concept for integrating cobalt materials into the metal plug to the source/drain contact, such as the Co-plug/CoTi/CoSix structure so that Co is considered the most potential material for future contact structures. In our research, we propose Co silicide on n-Si substrate formed by atomic layer deposition (ALD) deposited Co and subsequent rapid thermal annealing (RTA) as the contact silicide for aggressively scaled contact technology. ALD-Co silicide formed by RTA exhibits the best contact resistivity (ρc) with crystallinity in the CoSi2 phase, a highly oriented crystal structure, and a smooth surface. Compared to PVD-Co silicide, ALD-Co silicide significantly reduces contact resistivity. The major difference between ALD and PVD-Co silicide is the interface roughness between the silicide and Si substrate. The significantly reduced interface roughness in ALD-Co silicide, which makes the roughness-induced scattering effect less pronounced, thus reducing ρc. This suggests that ALD-Co silicide has potential as the contact silicide beyond the 5 nm technology node.
In order to surpass the material limits of silicon, the integration of germanium (Ge) and germanium tin (GeSn) materials with high carrier mobility and potential for silicon circuit integration into the source and drain of transistors has garnered significant attention. However, there is a rather severe Fermi-level pinning effect on Ge that must be overcome to achieve low contact resistivity. Most research has focused on direct formation of germanides to improve this effect, with the hope of further reducing contact resistivity by improving germanide crystal quality, uniformity, and interface roughness between germanide and Ge substrate. Chapters 3 to 4 of this thesis mainly focus on developing metal contact technology methods for Ge-based materials to achieve excellent contact resistivity. In chapter 3, the benefits of cobalt deposition by ALD systems to improve contact resistivity are discussed. ALD-Co is deposited on n-Ge film and further annealed to form cobalt germanide by laser thermal annealing (LTA) or rapid thermal annealing. We observed that the ALD-Co germanide formed under laser thermal annealing not only has excellent interface quality with the n-Ge, but also achieves atomic-level flatness. Co-germanide exhibits a single crystal thin film of CoGe2, demonstrating superior contact resistivity characteristics compared to the RTA sample and improving the contact resistivity. In chapter 4, the ohmic contacts exhibited by Yb stanogermanides via α-GeSn/Yb/n-GeSn and SiO2/Yb/n-GeSn structures annealed with RTA to mitigate the Fermi-level pinning effect were studied. Nevertheless, the α-GeSn/Yb/n-GeSn structure demonstrated superior contact characteristics due to the smaller Schottky barrier height (ΦBN) and smoother surface roughness resulting in lower ρc. By combining these promising properties, Yb stanogermanide formed with an α-GeSn capping layer qualifies for emerging GeSn contact technology.
Finally, in Chapter 5, in view of the integration of tunnel field-effect transistor (TFET) with CMOS technology, research has focused on improving its turn-on current and ambipolar current so that its subthreshold swing (SS) can be less than 60 mV/dec. This thesis presents a new n-TFET structure (P-I-M TFET) that replaces the traditional semiconductor material at the drain with metal silicide to enhance device performance while simplifying the process. According to the TCAD simulation results, by employing metal silicide at the drain with a proper work function (WF) of 4.25 eV, the P-I-M TFET structure demonstrates superior characteristics compared to the traditional P-I-N TFET structure with much improved OFF-state current and suppressed ambipolar effect, respectively, due to reduced band-to-band tunneling and lower Shockley-Read-Hall recombination rate, resulting in the subthreshold swing improvement. The optimal metal work function index for the drain is 4.25 eV, resulting in the best performance. However, the process window must be evaluated for changes in the metal work function. The research findings suggest that the allowable metal work function change (process window) for the PIM-TFET is 0.15 eV, resulting in better performance than traditional tunneling transistors. To summarize, the P-I-M TFET is very appropriate to apply in green electronics with higher performance and lower cost.

中文摘要 i
Abstract iii
致謝 vi
Contents viii
Figure Captions xii
Table List xviii
Chapter 1 Introduction 1
1-1 Background 1
1-2 Realization of Ultra-Low Contact Resistivity 8
1-2.1 Realization Extremely High Dopants Concentration at the Metal/Semiconductor Interface 8
1-2.2 Mitigation of Fermi Level Pinning Effect 11
1-2.3 Crystallinity and Uniformity of Metal-Silicide or Germanide 14
1-3 Advanced Tunneling Transistor with Asymmetric Source and Drain Technology 18
1-3.1 Tunnel Field Effect Transistor (TFET) 18
1-3.2 Principle of Tunnel FET 21
1-3.3 Optimizing Low Turn-On Current at Source Side 24
1-3.4 Suppressing Ambipolar Effect at Drain Side 30
1-4 Organization of the Thesis 32
1-5 References 33
Chapter 2 Through Atomic Layer Deposited Cobalt and Subsequent Annealing to Form Co Silicide with Low Contact Resistivity 45
2-1 Prospects for ALD Cobalt Silicide 45
2-2 The Co Silicide Formation by PVD or ALD and Subsequent Rapid Thermal Annealing 47
2-3 The Film Characteristics and Analysis of PVD-Co and ALD-Co Silicide 48
2-3.1 Annealing Temperature on Properties of ALD-Co Silicide 48
2-3.2 Properties Comparison Between ALD-Co and PVD-Co Silicide 52
2-4 Summary 55
2-5 References 55
Chapter 3 Nearly Epitaxial Co Germanide with Low-Resistivity Formed by Atomic Layer Deposited Cobalt and Laser Thermal Annealing 58
3-1 Prospects for ALD-Co Germanide by Laser Thermal Annealing 58
3-2 The Co Germanide Formation by ALD-Co and Subsequent Rapid Thermal Annealing or Laser Thermal Annealing 60
3-3 The Contact Characteristics and Analysis of ALD-Co Germanide 61
3-3.1 Properties of ALD-Co Germanide Formed by Rapid Thermal Annealing 61
3-3.2 Properties of ALD-Co Germanide Formed by Laser Thermal Annealing 64
3-4 Summary 69
3-5 References 69
Chapter 4 Yb Stanogermanide Formation with Low-Contact Resistivity 73
4-1 Fermi Level Depinning on n-GeSn by Yb Stanogermanide 73
4-2 The Yb Stanogermanide Formation by Capping Layers and Subsequent Rapid Thermal Annealing 74
4-3 Contact Characteristics and Analysis of Yb Stanogermanide 75
4-3.1 Electrical Characteristics Comparison of Yb Stanogermanide Contact Between SiO2 and α-GeSn Capping Layer 75
4-3.2 Physical Characteristics Comparison of Yb Stanogermanide Contact Between SiO2 and α-GeSn Capping Layer 79
4-4 Summary 84
4-5 References 84
Chapter 5 Modulating Metal Work Function at Drain Side to Improve Swing and Ambipolar Effect for Novel Tunnel FET by Design and Simulation 88
5-1 A Promising Novel Structure for Tunnel FET 88
5-2 Simulation Design of Device Structure 89
5-3 Discussion on Subthreshold Swing and Ambipolar Effect of Device 92
5-4.1 Performances Comparison of P-I-N and P-I-M TFET 92
5-4.2 Effect of Metal Work Function at Drain Side on Device Performance for P-I-M TFET 98
5-4 Summary 103
5-5 References 104
Chapter 6 Conclusions and Further Recommendations 107
6.1 Conclusions 107
6.2 Further Recommendations 108
Publication List 109
Vita 111

Chapter 1
[1.1] H. Iwai, T. Ohguro, and Sh. Ohmi, “NiSi salicide technology for scaled CMOS,” Microelectronic Engineering, vol. 60, no. 1, pp. 157–169, 2002, doi: https://doi.org/10.1016/S0167-9317(01)00684-0.
[1.2] T. Ohguro, S. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, Y. Ushiku, T. Yoshitomi, M. Ono, M. Saito, and Hiroshi Iwai, “Analysis of resistance behavior in tiand Ni-salicided polysilicon films,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2305–2317, 1994, doi: 10.1109/16.337443.
[1.3] N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L. S. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B.J. Pawlak, R. Rooyackers, T. Schulz, K.T. San, N.J. Son, M. J. H. Van Dal, P. Verheyen, K. von Arnim, L. Witters, K. De Meyer, S. Biesemans, and M. Jurczak, “Multi-gate devices for the 32 nm technology node and beyond,” Solid-State Electronics, vol. 52, no. 9, pp.1291–1296, 2008, doi: 10.1109/ESSDERC.2007.4430899.
[1.4] H. Yu, M. Schaekers, E. Rosseel, A. Peter, J. G. Lee, W. B. Song, S. Demuynck, T. Chiarella, L-Å. Ragnarsson, S. Kubicek, J. Everaert, N. Horiguchi, K. Barla, D. Kim, N. Collaert1, A. V. Y. Thean, and K. De Meyer, “1.5×10-9 Ω·cm2 contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation, Int. Electron Devices Meeting Dig., pp. 592–595, 2015, doi: 10.1109/IEDM.2015.7409753.
[1.5] H. Yu, M. Schaekers, S. A. Chew, J. L. Everaert, A. Dabral, G. Pourtois, N. Horiguchi, D. Mocuta, N. Collaert, and K. D. Meyer, “Titanium (germano-)silicides featuring 10-9 Ω∙cm2 contact resistivity and improved compatibility to advanced CMOS technology,” Int. Workshop on Junction Tech. (IWJT), pp. 1–5, 2018, doi: 10.1109/IWJT.2018.8330298.
[1.6] A. V. Y Thean, D. Yakimets, T. H. Bao, P. Schuddinck, S. Sakhare, M. G. Bardon, A. S. Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, and N. Collaert, “Vertical device architecture for 5nm and beyond: device & circuit implications,” Symp. VLSI Tech. Dig., pp. T26–T27, 2015, doi: 10.1109/VLSIT.2015.7223689.
[1.7] Y. Wang, “Laser spike annealing resolves sub-20 nm logic device manufacturing challenges,” Solid-State Tech., vol. 57, no. 8, pp. 16–20, 2014.
[1.8] H. Yu, M. Sehaekersl, S. Demuynekl, K. Barlal, A. Moeutal, N. Horiguehil, N. Collaertl, A. V. Y. Theanl, and K. D. Meyer, “MIS or MS? source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond,” Int. Workshop on Junction Tech. (IWJT), pp. 1–6, 2016, doi: 10.1109/IWJT.2016.7486665.
[1.9] S. Dev, M. Meena, P. H. Vardhan, and S. Lodha, “Statistical simulation study of metal grainorientation-induced MS and MIS contact resistivity variability for 7nm FinFETs,” IEEE Trans. Electron Devices, vol. 65, no. 8, pp. 3104–3111, 2018, doi: 10.1109/TED.2018.2841975.
[1.10] J Robertson, and L Lin, “Fermi level pinning in Si, Ge and GaAs systems – MIGS or defects?,” Int. Electron Devices Meeting Dig., pp. 119–122, 2009, doi: 10.1109/IEDM.2009.5424406.
[1.11] K. W. Ang, K. Majumdar, K. Matthews, C. D. Young, C. Kenney, C. Hobbs, P. D. Kirsch, R. Jammy, R. D. Clark, S. Consiglio, K. Tapily, Y. Trickett, G. Nakamura, C. S. Wajda, G. J. Leusink, M. Rodgers, and S. C. Gausepoh, “Effective schottky barrier height modulation using dielectric dipoles for source/drain specific contact resistivity improvement,” Int. Electron Devices Meeting Dig., pp. 439–442, 2012, doi: 10.1109/IEDM.2012.6479068.
[1.12] C. N. Ni, X. Li, S. Sharma, K. V. Rao, M. Jin, C. Lazik, V. Banthia, B. Colombeau, N. Variam, A. Mayur, H. Chung, R. Hung, and A. Brand, “Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET,” Symp. VLSI Tech. Dig., pp. T118–T119, 2015, doi: 10.1109/VLSIT.2015.7223711.
[1.13] E. Ko, J. Lee, H. Shin, S.Park, and Daehong Ko, “Comparison of strain characteristics and contact resistances of heavily phosphorus-doped Si formed by phosphorus implantation and in situ phosphorus-doped Si epitaxial growth,” Phys. Status Solidi A, vol. 1900989, pp. 1–6, 2020, doi: https://doi.org/10.1002/pssa.201900989.
[1.14] V. Mazzocchi, X. Pages, M. Py, J. P Barnes, K. Vanormelingen, L. Hutin, R. Truche, P. Vermont, M. Vinet, C. Le Royer, and K. Yckache, “Diffusion and activation of boron and phosphorus in pre-amorphized and crystalline germanium using ultra-fast spike anneal,” Int. Conference on Adv. Thermal Processing of Semiconductors, pp. 1–5, 2009, doi: 10.1109/RTP.2009.5373459.
[1.15] H. Yu, M. Schaekers, J. Zhang, L. L. Wang, J. L. Everaert, N. Horiguchi, Y. L. Jiang, D. Mocuta, N. Collaert, and K. D. Meyer, “TiSi(Ge) contacts formed at low temperature achieving around 2×10−9 Ω·cm2 contact resistivities to p-SiGe,” IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 500–505, 2017, doi: 10.1109/TED.2016.2642888.
[1.16] F. K. Hsueh, Y. J. Lee, K. L. Lin, M. I. Current, C. Y. Wu, and T. S. Chao, “Amorphous-layer regrowth and activation of P and As implanted Si by low-temperature microwave annealing,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 2088–2093, 2011, doi: 10.1109/TED.2011.2132801.
[1.17] Y. J. Lee, S. S. Chuang, C. I. Liu, F. K. Hsueh, P. J. Sung, H. C. Chen, C. T. Wu, K. L. Lin, J. Y. Yao, Y. L. Shen, M. L. Kuo, C. H. Yang, G. L. Luo, H. W. Chen, C. H. Lai, M. I. Current, C. Y. Wu, Y. M. Wan, T. Y. Tseng, C. Hu, and F. L. Yang, “Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and ultrathin 7.5nm Ni mono-germanide,” Int. Electron Devices Meeting Dig., pp. 531–516, 2012, doi: 10.1109/IEDM.2012.6479087.
[1.18] O. Gluschenkov, Z. Liu, H. Niimi, S. Mochizuki, J. Fronheiser, X. Miao, J. Li, J. Demarest, C. Zhang, C. Niu, B. Liu, A. Petrescu, P. Adusumilli, J. Yang, H. Jagannathan, H. Bu, and T. Yamashita, “FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys” Int. Electron Devices Meeting Dig., pp. 448–451, 2016, doi: 10.1109/IEDM.2016.7838437.
[1.19] W. Hsu, F. Wen, X. Wang, Y. Wang, A. Dolocan, A. Roy, T. Kim, E. Tutuc, and Sanjay K. Banerjee, “Laser spike annealing for shallow junctions in Ge CMOS,” IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 346–352, 2017, doi: 10.1109/TED.2016.2635625.
[1.20] C. Wang, C. Li, S. Huang, W. Lu, G. Yan, G. Lin, J. Wei, W. Huang, H. Lai, and S. Chen, “Low specific contact resistivity to n-Ge and well-behaved Ge n+/p diode achieved by implantation and excimer laser annealing,” Appl. Phys. Exp. vol. 6, no. 10, pp. 106501-1–106501-4, 2013, doi: 10.7567/APEX.6.106501.
[1.21] C. Y. Chang, F. A. Khaja, K. E Hollar, K. Rao, C. Lazik, M. Jin, H. Zhou, R. Hung, Y. C. Huang, H. Chung, A. Mayur, and N. Kim, “Ultra-low (1.2×10−9 Ω·cm2) p- Si0.55Ge0.45 contact resistivity (ρc) using nanosecond laser anneal for 7nm nodes and beyond,” Int. Workshop on Junction Tech. (IWJT), pp. 1–4, 2017, doi: 10.23919/IWJT.2017.7966504.
[1.22] H. Luth, “Solid surfaces, interfaces and thin films,” Springer Science & Business Media, pp.260–262, 2015, ISBN: 978-3-319-10756-1.
[1.23] R. Islam, G. Shine, and K. C. Saraswat, “Schottky barrier height reduction for holes by Fermi level depinning using metal/nickel oxide/silicon contacts,” Appl. Phys. Lett., vol. 105, no. 18, pp. 182103-1–182103-4, 2014, doi: https://doi.org/10.1063/1.4901193.
[1.24] T. Nishimura, K. Kita, and A. Toriumi, “Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface,” Appl. Phys. Lett., vol. 91, no. 12, pp. 123123-1–123123-3, 2007, doi: https://doi.org/10.1063/1.2789701.
[1.25] L. Lin, Y. Guo, and J. Robertson, “Metal silicide Schottky barriers on Si and Ge show weaker Fermi level pinning,” Appl. Phys. Lett., vol. 101, no. 5, pp. 052110-1–052110-4, 2012, doi: https://doi.org/10.1063/1.4742861.
[1.26] K. Martens, R. Rooyackers, A. Firrincieli, B. Vincent, R. Loo, B. De Jaeger, M. Meuris, P. Favia, H. Bender, B. Douhard, W. Vandervorst, E. Simoen, M. Jurczak, D. J. Wouters, and J. A. Kittl, “Contact resistivity and Fermi-level pinning in n-type Ge contacts with epitaxial Si-passivation,” Appl. Phys. Lett., vol. 98, no. 1, pp. 013504-1–013504-4, 2011, doi: https://doi.org/10.1063/1.3530437.
[1.27] M. Kobayashi, A. Kinoshita, K. Saraswat, H. S. P. Wong, and Y. Nishi, “Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal oxide-semiconductor field-effect-transistor application,” J. Appl. Phys., vol. 105, no. 2, pp. 023702-1–023702-7, 2009, doi: https://doi.org/10.1063/1.3065990.
[1.28] P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, and S. Lodha, “ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts,” Symp. VLSI Tech. Dig., pp. T83–T84, 2012, doi: 10.1109/VLSIT.2012.6242472.
[1.29] K. Y. Chen, C.C. Su, C. P. Chou, and Y. H. Wu, “Formation of ohmic contact with low contact resistance on N-GeSn by fermi level depinning using plasma treatment,” IEEE Electron Device Lett., vol. 37, no. 7, pp. 827–830, 2016, doi: 10.1109/LED.2016.2566809.
[1.30] Y. Tong, G. Han, B. Liu, Y. Yang, L. Wang, W. Wang, and Y. C. Yeo, “Ni(Ge1−xSnx) Ohmic contact formation on N-Type Ge1−xSnx using selenium or sulfur implant and segregation,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 746–752, 2013, doi: 10.1109/TED.2012.2233204.
[1.31] M. Mueller, Q. T. Zhao, C. Urban, C. Sandow, D. Buca, S. Lenk, S. Estévez, and S. Mantl, “Schottky-barrier height tuning of NiGe/n-Ge contacts using As and P segregation,” Mater. Sci. and Eng. B, vol. 154-155, pp. 168–171, 2008, doi: https://doi.org/10.1016/j.mseb.2008.09.037.
[1.32] H. Li, Y. Guo, and J. Robertson, “Face dependence of Schottky barriers heights of silicides and germanides on Si and Ge,” Scientific Reports, vol. 7, no. 16669, pp. 1–8, 2017, doi: 10.1038/s41598-017-16803-6.
[1.33] S. Zhu, J. Chen, M. F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565–567, 2004, doi: 10.1109/LED.2004.831582.
[1.34] Z. W. Zheng, T. C. Ku, M. Liu, and A. Chin, “Ohmic contact on n-type Ge using Yb-germanide,” Appl. Phys. Lett., vol. 101, no. 22, pp. 223501-1–223501-3, 2012, doi: https://doi.org/10.1063/1.4768700.
[1.35] K. Gallacher, P. Velha, D. J. Paul, I. MacLaren, M. Myronov, and D. R. Leadley, “Ohmic contacts to n-type germanium with low specific contact resistivity,” Appl. Phys. Lett., vol. 100, no. 2, pp. 022113-1–022113-3, 2012, doi: https://doi.org/10.1063/1.3676667.
[1.36] H. J. Ahn, J. Moon, Y. Seo, T. I. Lee, C. K. Kim, W. S. Hwang, H. Y. Yu, and B. J. Cho, “Formation of low-resistivity nickel germanide using atomic layer deposited nickel thin film,” IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2599–2602, 2017, doi: 10.1109/TED.2017.2694456.
[1.37] H. Tanaka, T. Isogai, T. Goto, A. Teramoto, S. Sugawa, and T. Ohmi, “Low contact resistivity with low silicide/p+-silicon Schottky barrier for high-performance p-channel metal–oxide–silicon field effect transistors,” Jpn. J. Appl. Phys., vol. 49, no. 4S, pp. 04DA03-1–04DA03-5, 2010, doi: 10.1143/JJAP.49.04DA03.
[1.38] V. K. Dugaev, and V. I. Litvinov, “Electric-current transmission through the contact of two metals,” Physical Review B, vol. 52, no. 7, pp. 5306–5312, 1995, doi: https://doi.org/10.1103/PhysRevB.52.5306.
[1.39] H. Y. Chen, C. Y. Lin, M. C. Chen, C. C. Huang, and C. H. Chien, “Nickel silicide formation using pulsed laser annealing for nMOSFET performance improvement,” J. Electrochemical Soc., vol. 158, no. 8, pp. H840–H845, 2011, doi: 10.1149/1.3601849.
[1.40] M. Shayesteh, K. Huet, I. T. Tresonne, R. Negru, C. L. M. Daunt, N. Kelly, D. O’Connell, R. Yu, V. Djara, P. B. Carolan, N. Petkov, and Ray Duffy, “Atomically flat low-resistive germanide contacts formed by laser thermal anneal,” IEEE Trans. Electron Devices, vol. 60, no.7, pp. 2178–2185, 2013, doi: 10.1109/TED.2013.2263336.
[1.41] S. Datta, “Recent advances in high performance CMOS transistors: from planar to non-planar,” Electrochemical Soc. Interface, vol. 22, no.1, pp. 41–46, 2013, doi: 10.1149/2.F04131if.
[1.42] S. H. Kim1, H. Kam, C. Hu and T. J. K. Liu, “Germanium-source tunnel field effect transistors with record high ION/IOFF,” Symp. VLSI Tech. Dig., pp. 178–179, 2009, ISBN: 978-1-4244-3308-7.
[1.43] J. H. Seo, Y. J. Yoon, S. Lee, J. H. Lee, S. Cho, and I. M. Kang, “Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET),” Current Appl. Phys., vol. 15, no. 3, pp. 208–212, 2015, doi: https://doi.org/10.1016/j.cap.2014.12.013.
[1.44] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤ 50 mV/decade subthreshold swing,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1054–1506, 2011, doi: 10.1109/LED.2011.2165331.
[1.45] T. N. Theis, “New devices for computing,” Silicon Nanoelectronics Workshop, 2014, doi: 10.1109/SNW.2014.7348525.
[1.46] R. Rita, V. Anne, S. V. Anne, M. W. Amey, S. Eddy, D. Katia, L. C. Sabrina, D. Marc, B. George, L. Roger, H. Andriy, V. Tom, H. Cedric, C. Nadine, and V. Y. T. Aaron, “Ge source vertical tunnel FETs using a novel replacement source integration scheme,” IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4032–4039, 2014, doi: 10.1109/TED.2014.2365142.
[1.47] H. Wang, Y. Liu, M. Liu, Q. Z, C. Zhang, X. Ma, J. Zhang, Y. Hao, and G. Han, “Performance improvement in novel germanium-tin/germanium heterojunction enhanced p-channel tunneling field-effect transistor,” Superlattices and Microstructures, vol. 383, pp. 401–410, 2015, doi: https://doi.org/10.1016/j.spmi.2015.03.030.
[1.48] Y. Yang, G. Han, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low, and Y. C. Yeo, “Germanium-tin p-channel tunneling field-effect transistor: device design and technology demonstration,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4048–4055, 2013, doi: 10.1109/TED.2013.2287031.
[1.49] Y. Yang, S. Su, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low, G. Zhang, C. Xue, B. Cheng, G. Han, and Y. C. Yeo, “Towards direct band-to-band tunneling in p-channel tunneling field effect transistor (TFET): technology enablement by germanium-tin (GeSn),” in IEDM Tech. Dig., pp. 379–382, 2012, doi: 10.1109/IEDM.2012.6479053.
[1.50] S. Datta, H. Liu, and V. Narayanan, “Tunnel FET technology: A reliability perspective,” Microelectronics Reliability, vol. 54, no. 5, pp. 861–874, 2014, doi: https://doi.org/10.1016/j.microrel.2014.02.002.
[1.51] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches.” Nature, vol. 479, pp. 329–337, 2011, doi: 10.1038/nature10679.
[1.52] S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta, “Temperature-dependent I–V characteristics of a Vertical In0.53Ga0.47 as tunnel FET,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 564–566, 2010, doi: 10.1109/LED.2010.2045631.
[1.53] U. E. Avci, B. C. Kung, A. Agrawal, G. Dewey, V. Le, R. Rios, D. H. Morris, S. Hasan, R. Kotlyar, J Kavalieros, and I. A. Young, “Study of TFET non-ideality effects for determination of geometry and defect density requirements for Sub-60mV/dec Ge TFET,” in IEDM Tech. Dig., pp. 891–894, 2015, doi: 10.1109/IEDM.2015.7409828.
[1.54] R. Pandey, S. Mookerjea, and Suman Datta, “Opportunities and challenges of tunnel FETs,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp.2128–2138, 2016, doi: 10.1109/TCSI.2016.2614698.
[1.55] I. A. Young, U. E. Avci, and D. H. Morris, “Tunneling Field Effect Transistors: Device and Circuit Considerations for Energy Efficient Logic Opportunities,” in IEDM Tech. Dig., pp. 600–603, 2015, doi: 10.1109/IEDM.2015.7409755.
[1.56] U. E. Avci, D. H. Morris, and I. A. Young, “Tunnel field-effect transistors: prospects and challenges,” J. Electron. Devices Society, vol. 3, no. 3, pp.88–95, 2015, doi: 10.1109/JEDS.2015.2390591.
[1.57] M. S. Ram, and D. B. Abdi, “Dopingless PNPN tunnel FET with improved performance: design and analysis,” Superlattices and Microstructures, vol. 82, pp. 430–437, 2015, doi: https://doi.org/10.1016/j.spmi.2015.02.024.
[1.58] W. Cao, C. J. Yao, G. F. Jiao, D. Huang, H. Y. Yu, and M. F. Li, “Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 2122–2126, 2011, doi: 10.1109/TED.2011.2144987.
[1.59] R. Rooyackers, A. Vandooren, A. S. Verhulst, A. Walke, K. Devriendt, S. Locorotondo, M. Demand, G. Bryce, R. Loo, A. Hikavyy, T. Vandeweyer, C. Huyghebaert, N. Collaert, and A. Thean, “A new complementary hetero-junction vertical tunnel-FET integration scheme,” in IEDM Tech. Dig., pp. 92–95, 2013, doi: 10.1109/IEDM.2013.6724558.
[1.60] T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, “Double-gate strained-ge heterostructure tunneling FET (TFET) with record high drive currents and < 60mV/dec subthreshold slope,” in IEDM Tech. Dig., pp. 2008, doi: 10.1109/IEDM.2008.4796839.
[1.61] E. H. Toh, G. H. Wang, G. Samudra, and Y. C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high-performance applications,” J. Appl. Phys., vol. 103, no. 10, pp. 104504-1－104504-5, 2008, doi: https://doi.org/10.1063/1.2924413.
[1.62] D. B. Abdi, and M. J. Kumar, “PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis,” Superlattices and Microstructures, vol. 86, pp. 121–125, 2015, doi: https://doi.org/10.1016/j.spmi.2015.07.045.

Chapter 2
[2.1] D. Gall, “Electron mean free path in elemental metals,” J. Appl. Phys., vol. 119, no. 8, p. 085101, Feb. 2016, doi: 10.1063/1.4942216.
[2.2] N. Breil, D. Shemesh, J. Fernandez, R. Hung, N. Bekiaris, J. Tseng, M. Naik, J. H. Park, J. Bakke, A. Kumar, K. Nafisi, A. Litman, A. Karnieli, V. Kuchik, A. Wachs, N. Khasgiwale, and M. Chudzik, “Electron beam detection of cobalt trench embedded voids enabling improved process control for middle-of-line at the 7 nm node and beyond,” in IEDM Tech. Dig., Dec. 2017, pp. 349–352, doi: 10.1109/IEDM.2017.8268391.
[2.3] R. Hung, J. H. Park, T. H. Ha, M. Lee, W. Hou, J. Lei, J. R. Bakke, S. Sharma, K. R. Sharma, N. S. Kim, E. Yeh, and A. Wachs, “Extreme contact scaling with advanced metallization of cobalt,” in Proc. Intl. Interconnect Technol. Conf., Jun. 2018, pp. 30–32, doi: 10.1109/IITC.2018.8430434.
[2.4] J. Koike, M. Hosseini, H. T. Hai, D. Ando, and Y. Sutou, “Material innovation for MOL, BEOL, and 3D integration,” in IEDM Tech. Dig., Dec. 2017, pp. 725–728, doi: 10.1109/IEDM.2017.8268485.
[2.5] H. Kim, J. Yoon, and H.-B.-R. Lee, “Atomic layer deposition for nanoscale contact applications,” in Proc. Intl. Interconnect Technol. Conf., May 2011, pp. 1–3, doi: 10.1109/IITC.2011.5940260.
[2.6] C. N. Ni, X. Li, S. Sharma, K. V. Rao, M. Jin, C. Lazik, V. Banthia, B. Colombeau, N. Variam, A. Mayur, H. Chung, R. Hung, and A. Brand, “Ultra-low contact resistivity with highly doped Si: P contact for nMOSFET,” in Proc. Symp. VLSI Technol., Jun. 2015, pp. 118–119, doi: 10.1109/VLSIT.2015.7223711.
[2.7] S. M. George, “Atomic layer deposition: An overview,” Chem. Rev., vol. 110, no. 1, pp. 111–131, Nov. 2009, doi: 10.1021/cr900056b.
[2.8] H. Jun Ahn, J. Moon, Y. Seo, T. I. Lee, C. K. Kim, W. S. Hwang, H. Yong Yu, and B. J. Cho, “Formation of low-resistivity nickel germanide using atomic layer deposited nickel thin film,” IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2599–2603, Jun. 2017, doi: 10.1109/TED.2017.2694456.
[2.9] M. R. Baklanov, I. A. Badmaeva, R. A. Donaton, L. L. Sveshnikova, W. Storm, and K. Maex, “Kinetics and mechanism of the etching of CoSi2 in HF-based solutions,” J. Electrochem. Soc., vol. 143, no. 10, pp. 3245–3251, Oct. 1996, doi: 10.1149/1.1837192.
[2.10] V. K. Dugaev, V. I. Litvinov, and P. P. Petrov, “Electric-current transmission through the contact of two metals,” Phys. Rev. B, Condens. Matter, vol. 52, no. 7, pp. 5306–5312, Aug. 1995, doi: 10.1103/PhysRevB.52.5306.
[2.11] M. Shayesteh, K. Huet, I. Toqué-Tresonne, R. Negru, C. L. M. Daunt, N. Kelly, D. O. Connell, R. Yu, V. Djara, P. B. Carolan, N. Petkov, and R. Duffy, “Atomically flat low-resistive germanide contacts formed by laser thermal anneal,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2178–2185, Jul. 2013, doi: 10.1109/TED.2013.2263336.
[2.12] W. Hsu, X. Wang, F. Wen, Y. Wang, A. Dolocan, T. Kim, E. Tutuc, and S. K. Banerjee, “High phosphorus dopant activation in germanium using laser spike annealing,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1088–1091, Sep. 2016, doi: 10.1109/LED.2016.2587829.

Chapter 3
[3.1] Z. J. Gong, S. K. Wang, X. Yang, B. Sun, W. Zhao, H. D. Chang, and H. G. Liu, “Schottky barrier height modulation in metal/n-Ge system,” in Proc. IEEE Int. Conf. Solid-State Integr. Circuit Technol., Oct. 2014, pp. 1–3, doi: 10.1109/ICSICT.2014.7021633.
[3.2] J. Y. J. Lin, A. M. Roy, A. Nainani, Y. Sun, and K. C. Saraswat, “Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height,” Appl. Phys. Lett., vol. 98, no. 9, p.092113, Mar. 2011, doi: 10.1063/1.3562305.
[3.3] P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M. C. Abraham, S. Kapadia, U. Ganguly, and S. Lodha, “ZnO: An attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 2011–2012, doi: 10.1109/VLSIT.2012.6242472.
[3.4] H. Li, Y. Guo, and J. Robertson, “Face dependence of Schottky barriers heights of silicides and germanides on Si and Ge,” Sci. Rep., vol. 7, p. 16669, Nov. 2017, doi: 10.1038/s41598-017-16803-6.
[3.5] K. Gallacher, P. Velha, D. J. Paul, I. MacLaren, M. Myronov, and D. R. Leadley, “Ohmic contacts to n-type germanium with low specific contact resistivity,” Appl. Phys. Lett., vol. 100, no. 2, p. 022113, Jan. 2012, doi: 10.1063/1.3676667.
[3.6] Q. Zhang, N. Wu, T. Osipowicz, L. K. Bera, and C. Zhu, “Formation and thermal stability of nickel germanide on germanium substrate,” Jpn. J. Appl. Phys., vol. 44, no. 45, pp. L1389–L1391, Oct. 2005, doi: 10.1143/JJAP.44.L1389.
[3.7] C. P. Chou, H. H. Chang, and Y. H. Wu, “Enabling low contact resistivity on n-Ge by implantation after Ti germanide,” IEEE Electron Device Lett., vol. 39, no. 1, pp. 91–94, Jan. 2018, doi: 10.1109/led.2017.2774502.
[3.8] N. Yoshida, S. Hassan, W. Tang, Y. Yang, W. Zhang, S. C. Chen, L. Dong, H. Zhou, M. Jin, M. Okazaki, J. Park, N. Bekiaris, R. Hung, J. Zhou, Y. Lei, P. Ma, X. Tang, T. Miyashita, N. Kim, and E. Yieh, “Highly conductive metal gate fill integration solution for extremely scaled RMG stack for 5 nm & beyond,” in IEDM Tech. Dig., Dec. 2017, pp. 541–544, doi: 10.1109/IEDM.2017.8268439.
[3.9] J. Koike, M. Hosseini, H. T. Hai, D. Ando, and Y. Sutou, “Material innovation for MOL, BEOL, and 3D integration,” in IEDM Tech. Dig., Dec. 2017, pp. 725–728, doi: 10.1109/IEDM.2017.8268485.
[3.10] M. Shayesteh, K. Huet, I. Toqué-Tresonne, R. Negru, C. L. M. Daunt, N. Kelly, D. O. Connell, R. Yu, V. Djara, P. B. Carolan, N. Petkov, and R. Duffy, “Atomically flat low-resistive germanide contacts formed by laser thermal anneal,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2178–2185, Jul. 2013, doi: 10.1109/TED.2013.2263336.
[3.11] S. H. Huang, F. L. Lu, W.-L. Huang, C. H. Huang, and C. W. Liu, “The ~3×1020 cm−3 electron concentration and low specific contact resistivity of phosphorus-doped Ge on Si by in-situ chemical vapor deposition doping and laser annealing,” IEEE Trans. Electron Devices, vol. 36, no. 11, pp. 1114–1117, Nov. 2015, doi: 10.1109/LED.2015.2478916.
[3.12] F. L. Lu, C. E. Tsai, I. H. Wong, C. T. Lu, and C. W. Liu, “Dopant recovery in epitaxial Ge on SOI by laser annealing with device applications,” IEEE Trans. Electron Devices, vol. 65, no. 7, pp. 2925–2931, Jul. 2018, doi: 10.1109/TED.2018.2834382.
[3.13] H. J. Ahn, J. Moon, Y. Seo, T. I. Lee, C. K. Kim, W. S. Hwang, H. Y. Yu, and B. J. Cho, “Formation of low-resistivity nickel germanide using atomic layer deposited nickel thin film,” IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2599–2603, Jun. 2017, doi: 10.1109/TED.2017.2694456.
[3.14] J. R. Wu, Y. H. Wu, C. Y. Hou, M. L. Wu, C. C. Lin, and L. L. Chen, “Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions,” Appl. Phys. Lett., vol. 99, no. 25, p. 253504, Nov. 2011, doi: 10.1063/1.3666779.
[3.15] S. Zhu, C. Detavernier, R. L. V. Meirhaeghe, F. Cardon, G. P. Ru, X. P. Qu, and B. Z. Li, “Electrical characteristics of CoSi2/n-Si(1 0 0) Schottky barrier contacts formed by solid state reaction,” Solid State Electron., vol. 44, no. 10, pp. 1807–1818, Oct. 2000, doi: 10.1016/S0038-1101(00)00127-1.
[3.16] M. Witmer, D. L. Smith, P. W. Lew, and M. A. Nicolet, “Electrical characteristics of palladium silicide,” Solid State Electron., vol. 31, no. 3, pp. 570–580, Mar. 1978, doi: 10.1016/0038-1101(78)90029-1.
[3.17] G. P. Ru, B. Z. Li, G. B. Jiang, X. P. Qu, J. Liu, R. L. V. Meirhaeghe, and F. Cardon, “Surface and interface morphology of CoSi2 films formed by multilayer solid-state reaction,” Mater. Characterization, vol. 48, nos. 2–3, pp. 229–235, Apr. 2002, doi: 10.1016/S1044-5803(02)00252-8.
[3.18] H. Yu, M. Schaekers, A. Peter, G. Pourtois, E. Rosseel, J. G. Lee, W. B. Song, K. M. Shin, J. L. Everaert, S. A. Chew, S. Demuynck, D. Kim, K. Barla, A. Mocuta, N. Horiguchi, A. V. Y. Thean, N. Collaert, and K. D. Meyer, “Titanium silicide on Si:P with precontact amorphization implantation treatment: contact resistivity approaching 1×10−9 Ohm-cm2,” IEEE Trans. Electron Devices, vol. 63, no. 12, pp. 4632–4640, Dec. 2016, doi: 10.1109/TED.2016.2616587.

Chapter 4
[4.1] J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, and M. Vinet, “Considerations for efficient contact resistivity reduction via Fermi level depinning Impact of MIS contacts on 10 nm node nMOSFET DC characteristics,” in Proc. Symp. VLSI Technol., Jun. 2015, pp. 116–117, doi: 10.1109/VLSIT.2015.7223710.
[4.2] M. Kobayashi, A. Kinoshita, K. Saraswat, H. S. P. Wong, and Y. Nishi, “Fermi level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET,” in Proc. Symp. VLSI Technol., Jun. 2008, pp. 54–55, doi: 10.1109/VLSIT.2008.4588561.
[4.3] Y. Zhou, W. Han, Y. Wang, F. Xiu, J. Zou, R. K. Kawakami, and K. L. Wang, “Investigating the origin of Fermi level pinning in Ge Schottky junctions using epitaxially grown ultrathin MgO films,” Appl. Phys. Lett., vol. 96, no. 10, p. 102103, 2010, doi: 10.1063/1.3357423.
[4.4] P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M. C. Abraham, S. Kapadia, U. Ganguly, and S. Lodha, “ZnO: An attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 2011–2012, doi: 10.1109/VLSIT.2012.6242472.
[4.5] J. Y. J. Lin, A. M. Roy, A. Nainani, Y. Sun, and K. C. Saraswat, “Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height,” Appl. Phys. Lett., vol. 98, no. 9, p. 092113, 2011, doi: 10.1063/1.3562305.
[4.6] L. Lin, Y. Guo, and J. Robertson, “Metal silicide Schottky barriers on Si and Ge show weaker Fermi level pinning,” Appl. Phys. Lett., vol. 101, no. 5, p. 052110, 2012, doi: 10.1063/1.4742861.
[4.7] C. H. Wu, B. F. Hung, A. Chin, S. J. Wang, F. Y. Yen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide,” IEEE Electron Device Lett., vol. 27, no. 6, pp. 454–456, Jun. 2006, doi: 10.1109/LED.2006.874778.
[4.8] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004, doi: 10.1109/LED.2004.831582.
[4.9] Z. W. Zheng, T.-C. Ku, M. Liu, and A. Chin, “Ohmic contact on n-type Ge using Yb-germanide,” Appl. Phys. Lett., vol. 101, no. 22, p. 223501, 2012, doi: 10.1063/1.4768700.
[4.10] Y. Tong, G. Han, B. Liu, Y. Yang, L. Wang, W. Wang, and Y. C. Yeo, “NiGe1−x Snx ohmic contact formation on N-type Ge1−x Snx using selenium or sulfur implant and segregation,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 746–752, Feb. 2013, doi: 10.1109/TED.2012.2233204.
[4.11] C. W. Lee, Y. H. Wu, C. H. Hsieh, and C. C. Lin, “Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb2O3-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness,” Appl. Phys. Lett., vol. 105, no. 20, p. 203508, 2014, doi: 10.1063/1.4902119.
[4.12] Y. C. Fang, K. Y. Chen, C. H. Hsieh, C. C. Su, and Y. H. Wu, “N-MOSFETs formed on solid phase epitaxially grown GeSn film with passivation by oxygen plasma featuring high mobility,” ACS Appl. Mater. Interfaces, vol. 7, no. 48, pp. 26374–26380, 2015, doi: 10.1021/acsami.5b08518.
[4.13] J. Y. J. Lin, A. M. Roy, and K. C. Saraswat, “Reduction in specific contact resistivity to n+ Ge using TiO2 interfacial layer,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1541–1543, Nov. 2012, doi: 10.1109/LED.2012.2214758.
[4.14] K. Martens, A. Firrincieli, R. Rooyackers, B. Vincent, R. Loo, S. Locorotondo, E. Rosseel, T. Vandeweyer, G. Hellings, B. De Jaeger, M. Meuris, P. Favia, H. Bender, B. Douhard, J. Delmotte, W. Vandervorst, E. Simoen, G. Jurczak, D. Wouters, and J. A. Kittl, “Record low contact resistivity to n-type Ge for CMOS and memory applications,” in IEDM Tech. Dig., 2010, pp. 18.4.1–18.4.4, doi: 10.1109/IEDM.2010.5703387.
[4.15] G. S. Kim, S. H. Kim, J. K. Kim, C. Shin, J. H. Park, K. C. Saraswat, B. J. Cho, and H. Y. Yu, “Surface passivation of germanium using SF6 plasma to reduce source/drain contact resistance in germanium n-FET,” IEEE Electron Device Lett., vol. 36, no. 8, pp. 745–747, Aug. 2015, doi: 10.1109/LED.2015.2440434.
[4.16] G. W. Peng, Y. P. Feng, A. C. H. Huan, M. Bouville, D. Z. Chi, and D. J. Srolovitz, “Mechanisms of silicon diffusion in erbium silicide,” Phys. Rev. B, vol. 75, no. 12, p. 125319, 2007, doi: 10.1103/PhysRevB.75.125319.
[4.17] Y. L. Jiang, Q. Xie, C. Detavernier, R. L. Van Meirhaeghe, G. P. Ru, X. P. Qu, B. Z. Li, and P. K. Chu, “Growth of pinhole-free ytterbium silicide film by solid-state reaction on Si(001) with a thin amorphous Si interlayer,” J. Appl. Phys., vol. 102, no. 3, p. 033508, 2007, doi: 10.1063/1.2767375.
[4.18] H. Y. Chen, C. Y. Lin, M. C. Chen, C. C. Huang, and C. H. Chien, “Nickel silicide formation using pulsed laser annealing for nMOSFET performance Improvement,” J. Electrochem. Soc., vol. 158, no. 8, pp. H840–H845, 2011, doi: 10.1149/1.3601849.
[4.19] W. C. Tsai, K. S. Chi, and L. J. Chen, “Growth of pinhole-free epitaxial Yb and Er silicide thin films on atomically clean (111) Si,” J. Appl. Phys., vol. 96, no. 9, p. 5353, 2004, doi: 10.1063/1.1769604.
[4.20] Y. Nishi and R. Doering, Eds., Handbook of Semiconductor Manufacturing Technology, 2nd ed. Boca Raton, FL, USA: CRC Press, 2007, pp. 10-1–10-52.

Chapter 5
[5.1] A. C. Seabaugh and Q. Zhang, “Low voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010, doi: 10.1109/JPROC.2010.2070470.
[5.2] A. Villalon, G. L. Carval, S. Martinie, C. L. Royer, M. A. Jaud, and S. Cristoloveanu, “Further insights in TFET operation,” IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2893–2898, Aug. 2014, doi: 10.1109/TED.2014.2325600.
[5.3] T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, and S. Clara, “Double gate strained Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2008, pp. 1–3, doi: 10.1109/IEDM.2008.4796839.
[5.4] A. Vladimirescu, Hraziia, A. Amara, and C. Anghel, “An analysis on the ambipolar current in Si double-gate tunnel FETs,” Solid State Electron., vol. 70, pp. 67–72, Apr. 2012, doi: https://doi.org/10.1016/j.sse.2011.11.009.
[5.5] E. H. Toh, G. H. Wang, G. Samudra, and Y. C. Yeoa, “Device physics and design of germanium tunneling field effect transistor with source and drain engineering for low power and high-performance applications,” J. Appl. Phys., vol. 103, no. 10, pp. 104504-1–104504-5, May 2008, doi: https://doi.org/10.1063/1.2924413.
[5.6] C. Anghel, Hraziia, A. Gupta, A. Amara, and A. Vladimirescu, “30 nm tunnel FET with improved performance and reduced ambipolar current,” IEEE Trans. Electron Devices, vol. 58, no. 6, pp. 1649–1654, Jun. 2011, doi: 10.1109/TED.2011.2128320.
[5.7] D. B. Abdi and M. J. Kumar, “PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis,” Superlattices Microstruct., vol. 86, pp. 121–125, Jul. 2015, doi: https://doi.org/10.1016/j.spmi.2015.07.045.
[5.8] J. Zhu et al., “Design and simulation of a novel graded channel heterojunction tunnel FET with high ION/IOFF ratio and steep swing,” IEEE Electron Device Lett., vol. 38, no. 9, pp. 1200–1203, Sep. 2017, doi: 10.1109/LED.2017.2734679.
[5.9] S. Garg and S. Saurabh, “Suppression of ambipolar current in tunnel FETs using drain pocket: Proposal and analysis,” Superlattices Microstruct., vol. 113, pp. 261–270, Jan. 2018, doi: https://doi.org/10.1016/j.spmi.2017.11.002.
[5.10] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011, doi: 10.1038/nature10679
[5.11] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Sinanowire n-type tunneling FETs with low subthreshold swing (≤ 50 mv/decade) at room temperature,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 437–439, Apr. 2011, doi: 10.1109/LED.2011.2106757.
[5.12] R. Rooyackers et al., “A new complementary hetero-junction vertical tunnel-FET integration scheme,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2013, pp. 4.2.1–4.2.4, doi: 10.1109/IEDM.2013.6724558.
[5.13] Z. Yang, “Tunnel field-effect transistor with an L-shaped gate,” IEEE Electron Device Lett., vol. 37, no. 7, pp. 839–842, Jul. 2016, doi: 10.1109/LED.2016.2574821.
[5.14] E. D. Kurniawan, S. Y. Yang, V. Thirunavukkarasu, and Y. C. Wu, “Analysis of Ge-Si heterojunction nanowire tunnel FET: Impact of tunneling window of band-to-band tunneling model,” J. Electrochem. Soc., vol. 164, no. 11, pp. E3354–3358, Jun. 2017, doi: 10.1149/2.0371711jes.
[5.15] H. Y. Chang, B. Adams, P. Y. Chien, J. Li, and J. C. S. Woo, “Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing,” IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 92–96, Jan. 2013, doi: 10.1109/TED.2012.2228006.
[5.16] H. Luan, H. N. Alshareef, P. S. Lysaght, H. R. Harris, and H. C. Wen, “Evaluation of tantalum silicon alloy systems as gate electrodes,” Appl. Phys. Lett., vol. 87, no. 21, pp. 212110-1–212110-3, Nov. 2005, doi: https://doi.org/10.1063/1.2126132.
[5.17] M. A. Taubenblatt and C. R. Helms, “Silicide and Schottky barrier formation in the Ti-Si and the Ti-SiOx-Si systems,” Appl. Phys. Lett., vol. 53, no. 9, pp. 6308–6315, May 1982, doi: https://doi.org/10.1063/1.331551.
[5.18] C. Lavoie, F. M. Heurle, and S. L. Zhang, “Silicides,” in Handbook of Semiconductor Manufacturing Technology, 2nd ed., vol. 10. Boca Raton, FL, USA: CRC Press, Jul. 2007, pp. 5–6.
[5.19] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Tunnel field-effect transistor without gate-drain overlap,” Appl. Phys. Lett., vol. 91, no. 5, pp. 053102-1–053102-3, Jul. 2007, doi: https://doi.org/10.1063/1.2757593.
[5.20] U. E. Avci, D. H. Morris, and I. A. Young, “Tunnel field-effect transistors: Prospects and challenges,” IEEE J. Electron Devices Soc., vol. 3, no. 3, pp. 88–95, May 2015, doi: 10.1109/JEDS.2015.2390591.