奈米尺寸的MOSFET，使用高介電閘層取代二氧化矽會使得載子遷移率下降，為了提升載子遷移率，通道材料的選擇及SiO2界面層的品質，扮演著重要的角色。本論文應用SiGe作為通道材料，以超晶格堆疊的方式提升載子遷移率及元件電特性。使用CF4電漿處理界面層，雖然可以降低EOT，但會有較高的介面陷阱及漏電流。因此應用O2、N2氣體電漿處理，來改善介面層的薄膜品質，提升載子遷移率。
在論文的第一部分中，使用磊晶成長Si/SiGe通道在FinFET電晶體上。SiGe材料相較於Si，具有較大的載子遷移率。比較單層SiGe通道與雙層的SiGe超晶格通道的電晶體特性，可以了解到SiGe超晶格通道結構，能在不產生應力的情況下，增加通道內Ge含量；中間插入一層應變矽以及Si-cap在通道上，能使Ge較不易擴散至界面，且能侷限載子於量子井內，因此能得到高的閘極電流、載子遷移率及較低的次臨界擺幅。以Si/SiGe super-lattice作為通道的鰭式電晶體，取得了汲極電流約為3.23x10-5A，開關電流的比例約為7個數量級，次臨界擺幅約為71 mV/dec，載子遷移率高達452 cm2/V-sec。
而在論文的第二部分中，在界面層使用CF4電漿處理能提高導通電流的情況下，結合O2或N2電漿處理，討論了對漏電流與介面缺陷修補的影響。維持CF4電漿處理的特性之下，使用O2電漿處理雖然擁有最佳的閘極電流和載子遷移率，但是漏電流大於Control元件。而使用N2電漿處理了，除了閘極電流及遷移率能獲得改善，且擁有最佳的漏電流。使用CF4+N2氣體電漿處理的鰭式電晶體元件取得了~2.7x10-5 A/cm2的閘極漏電流密度，開關電流的比例約為8個數量級，次臨界擺幅約為67.5 mV/dec，遷移率高達375 cm2/V-sec。

The carrier mobility of MOSFET with nano-scale is reduced by replacing SiO2 with high-k gate dielectric. Channel material selection and interfacial layer quality are crucial to enhance carrier mobility. In this thesis, SiGe is used as channel material, carrier mobility and electrical properties of FinFET are enhanced by super-lattice (SL) epitaxially. Although EOT can be reduced by IL with CF4 plasma treatment, the leakage and interface trap density are increased. Hence, O2 and N2 plasma are applied to improve the interface quality.
In the first part, Si/SiGe buried channel is epitaxially grown in layer-by-layer on SOI substrate. Strained SiGe is an attractive channel material beyond Si due to its higher carrier mobility. Electrical characteristics of FinFETs with SiGe and SiGe super-lattice(SL) buried channel are investigated and compared. The diffusion of GeOx can be suppressed by Si cap in SL structure, and the mobility can be enhanced by the strained Si/SiGe structure. FinFETs with SiGe SL buried channel demonstrate higher drain current of 3.23x10-5A, On/Off ratio of 7 orders and S.S of 71 mV/dec. A very high electron mobility of 452 cm2/V-sec is achieved for FinFET with Si/SiGe SL buried channel.
Effects of O2 and N2 plasma treatment on gate leakage and defect passivation in FinFET with CF4 plasma treated interfacial layer are studied in the second part. Higher drain current and mobility in FinFETs are achieved by combining CF4 together with O2 plasma treatments, but the leakage is too large. FinFETs treated by CF4 together with N2 plasma treatments show larger drain current, higher mobility and lower leakage current. A gate leakage current of 2.7x10-5 A/cm2, on/off ratio of 8 orders, S.S of 67.5 mV/dec, mobility of 375 cm2/V-sec in Si n-FinFET are achieved by CF4+N2 plasma treatments.

摘要 I
Abstract II
致謝 IV
目錄 V
表目錄 VIII
圖目錄 IX
第一章 緒論 1
1.1前言 1
1.2High-k介電材料 1
1.3高介電材料的選擇 2
1.4絕緣層覆矽基板 3
1.5鰭式電晶體 3
1.6矽鍺虛擬基板-應變通道 4
1.7臨界厚度 4
1.8差排 5
1.9氫氣電漿處理對鰭式通道的影響 5
1.10論文架構 6
第二章 元件製程與量測 18
2.1氧化鉿介電層應用在Gate First SOI n-FinFET製作流程 18
2.1.1晶片刻號 18
2.1.2磊晶矽鍺虛擬基板與鰭式矽鍺通道形成 18
2.1.3氫氣電漿對矽通道輪廓處理 19
2.1.4In-situ氣體電漿處理與閘極介電層沉積 19
2.1.5金屬閘電極的形成 19
2.1.6源極(Source)、汲極(Drain)、基極(Base)的形成 19
2.1.7鈍化層沉積 20
2.1.8接出金屬導線、燒結 20
2.2電性量測 20
2.2.1電容的量測 20
2.2.2金氧半電晶體的量測 20
第三章 磊晶矽鍺掩埋通道於矽在絕緣層上鰭式電晶體之電性研究 28
3.1研究動機與背景 29
3.2實驗流程 30
3.3實驗結果與討論 31
3.3.1元件在穿透式電子顯微鏡下的分析 31
3.3.2元件電容-電壓量測曲線 32
3.3.3元件閘極漏電流密度對電壓量測曲線 32
3.3.4元件汲極電流對閘極電壓量測曲線 33
3.3.5元件對汲極電流的影響 34
3.3.6元件轉導值對閘極電壓曲線 35
3.3.7元件載子遷移率特性 35
3.3.8元件可靠度特性 36
3.4結論 36
第四章 不同組合氣體電漿處理對單晶矽通道於絕緣層覆矽鰭式電晶體之電性研究 49
4.1研究動機與背景 49
4.2實驗流程 51
4.3實驗結果與討論 51
4.3.1元件電容-電壓量測曲線 51
4.3.2元件閘極漏電流密度對電壓量測曲線 52
4.3.3元件汲極電流對閘極電壓量測曲線 52
4.3.4元件對汲極電流的影響 53
4.3.5元件轉導值對閘極電壓曲線 53
4.3.6元件載子遷移率特性 54
4.3.7元件可靠度特性 54
4.4結論 55
第五章 結論與展望 66
5.1結論 66
5.2未來展望 67
參考文獻 68

[1] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, "Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology," IEEE transactions on very large scale integration (VLSI) systems, vol. 18, pp. 232-245, 2010.
[2] D. K. Schroder, Semiconductor material and device characterization: John Wiley & Sons, 2006.
[3] J. Stathis and D. DiMaria, "Reliability projection for ultra-thin oxides at low voltage," in Electron Devices Meeting, 1998. IEDM'98. Technical Digest., International, 1998, pp. 167-170.
[4] D. J. Frank, Y. Taur, and H.-S. Wong, "Generalized scale length for two-dimensional effects in MOSFETs," IEEE Electron Device Letters, vol. 19, pp. 385-387, 1998.
[5] D. Houghton, "Strain relaxation kinetics in Si1− x Gex/Si heterostructures," Journal of Applied Physics, vol. 70, pp. 2136-2151, 1991.
[6] M. Houssa, L. Pantisano, L.-Å. Ragnarsson, R. Degraeve, T. Schram, G. Pourtois, et al., "Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions," Materials Science and Engineering: R: Reports, vol. 51, pp. 37-85, 2006.
[7] H. S. Momose, S.-I. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, et al., "Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide," IEEE transactions on electron devices, vol. 45, pp. 691-700, 1998.
[8] L.-A. Ragnarsson, L. Pantisano, V. Kaushik, S.-I. Saito, Y. Shimamoto, S. De Gendt, et al., "The impact of sub monolayers of HfO2 on the device performance of high-k based transistors" in Electron Devices Meeting, 2003. IEDM'03 Technical Digest. IEEE International, 2003, pp. 4.2. 1-4.2. 4.
[9] R. People and J. Bean, "Calculation of critical layer thickness versus lattice mismatch for GexSi1−x/Si strained‐layer heterostructures," Applied Physics Letters, vol. 47, pp. 322-324, 1985.
[10] C. Manoj, M. Nagpal, D. Varghese, and V. R. Rao, "Device design and optimization considerations for bulk FinFETs," IEEE transactions on electron devices, vol. 55, pp. 609-615, 2008.
[11] B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, et al., "The device architecture dilemma for CMOS technologies: opportunities & challenges of Finfet over planar mosfet," in VLSI Technology, Systems, and Applications, 2009. VLSI-TSA'09. International Symposium on, 2009, pp. 80-81.
[12] D. Bhattacharya and N. K. Jha, "FinFETs: From devices to architectures," Advances in Electronics, vol. 2014, 2014.
[13] C. Kang, R. Choi, S. Song, B. Ju, M. Hussain, B. Lee, et al., "Effects of ALD TiN Metal Gate Thickness on Metal Gate/High-k Dielectric SOI FinFET Characteristics," in International SOI Conference, 2006 IEEE, 2006, pp. 135-136.
[14] T. Hayashida, K. Endo, Y. Liu, S.-I. O'uchi, T. Matsukawa, W. Mizubayashi, et al., "Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance," IEEE Transactions on Electron Devices, vol. 59, pp. 647-653, 2012.
[15] C. Y. Kang, J.-W. Yang, J. Oh, R. Choi, Y. J. Suh, H. Floresca, et al., "Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High-k Dielectric SOI FinFETs," IEEE Electron Device Letters, vol. 29, pp. 487-490, 2008.
[16] M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, et al., "High performance CMOS fabricated on hybrid substrate with different crystal orientations," in Electron Devices Meeting, 2003. IEDM'03 Technical Digest. IEEE International, 2003, pp. 18.7. 1-18.7. 4.
[17] I. Ok, H.-s. Kim, M. Zhang, C.-Y. Kang, S. J. Rhee, C. Choi, et al., "Metal gate-HfO2 MOS structures on GaAs substrate with and without Si interlayer," IEEE electron device letters, vol. 27, pp. 145-147, 2006.
[18] G. Vellianitis, M. J. van Dal, G. Boccardi, B. Duriez, F. C. Voogt, M. Kaiser, et al., "The Influence of TiN Thickness and SiO2 Formation Method on the Structural and Electrical Properties of TiN/HfO2/SiO2 Gate Stacks," IEEE Transactions on Electron Devices, vol. 56, pp. 1548-1553, 2009.
[19] R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, and P. Woerlee, "Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's," IEEE transactions on Electron Devices, vol. 42, pp. 109-115, 1995.
[20] D. J. Paul, "Si/SiGe heterostructures: from material and physics to devices and circuits," Semiconductor Science and Technology, vol. 19, p. R75, 2004.
[21] A. I. Kingon, M. Jon-Paul, and S. Streiffer, "Alternative dielectrics to silicon dioxide for memory and logic devices," Nature, vol. 406, p. 1032, 2000.
[22] Y. Wu, "Deep-Submicron-Devices Chapter 4," NTHU_2007, 2007.
[23] I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, "Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation," IEEE Electron Device Letters, vol. 12, pp. 181-183, 1991.
[24] N. Nickel, P. Mei, and J. Boyce, "On the nature of the defect passivation in polycrystalline silicon by hydrogen and oxygen plasma treatments," IEEE Transactions on Electron Devices, vol. 42, pp. 1559-1560, 1995.
[25] D. Kaplan, N. Sol, G. Velasco, and P. Thomas, "Hydrogenation of evaporated amorphous silicon films by plasma treatment," Applied Physics Letters, vol. 33, pp. 440-442, 1978.
[26] A. F. i Morral and P. R. i Cabarrocas, "Etching and hydrogen diffusion mechanisms during a hydrogen plasma treatment of silicon thin films," Journal of Non-Crystalline Solids, vol. 299, pp. 196-200, 2002.
[27] J.-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, and J. Bokor, "Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs," IEEE Electron Device Letters, vol. 24, pp. 186-188, 2003.
[28] T. Lee and S. K. Banerjee, "Reduced Gate-Leakage Current and Charge Trapping Characteristics of Dysprosium-Incorporated HfO2 Gate-Oxide n-MOS Devices," IEEE Transactions on Electron Devices, vol. 58, pp. 562-566, 2011.
[29] S.-i. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration," IEEE Transactions on Electron Devices, vol. 41, pp. 2357-2362, 1994.
[30] T. Ma, "Making silicon nitride film a viable gate dielectric," IEEE Transactions on Electron Devices, vol. 45, pp. 680-690, 1998.
[31] C. C. Yeo, B. J. Cho, F. Gao, S. Lee, M.-H. Lee, C.-Y. Yu, et al., "Electron mobility enhancement using ultrathin pure Ge on Si substrate," IEEE electron device letters, vol. 26, pp. 761-763, 2005.
[32] S. Ghosh and S. M. Han, "High-Mobility MOSFETs Fabricated on Continuous, Wafer-Scale Ge Films Epitaxially Grown on Si," IEEE Electron Device Letters, vol. 35, pp. 900-902, 2014.
[33] E. Kasper, K. Lyutovich, M. Bauer, and M. Oehme, "New virtual substrate concept for vertical MOS transistors," Thin Solid Films, vol. 336, pp. 319-322, 1998.
[34] M. Perego, G. Seguini, and M. Fanciulli, "Energy band alignment of HfO2 on Ge," Journal of applied physics, vol. 100, p. 093718, 2006.
[35] P.-J. Tzeng, S. Maikap, P.-S. Chen, Y.-W. Chou, C.-S. Liang, and L.-S. Lee, "Physical and reliability characteristics of Hf-based gate dielectrics on strained-Si1-xGex MOS devices," IEEE Transactions on Device and Materials Reliability, vol. 5, pp. 168-176, 2005.
[36] C. Liu and L. Chen, "SiGe/Si heterostructures," Encyclopedia of Nanoscience and Nanotechnology, HS Nalwa, Ed. Stevenson Ranch, CA: American Scientific, 2004.
[37] C. Wee, S. Maikop, and C.-Y. Yu, "Mobility-enhancement technologies," IEEE Circuits and Devices Magazine, vol. 21, pp. 21-36, 2005.
[38] S. Maikap, L. Bera, S. Ray, S. John, S. Banerjee, and C. Maiti, "Electrical characterization of Si/Si1−x Gex/Si quantum well heterostructures using a MOS capacitor," Solid-State Electronics, vol. 44, pp. 1029-1034, 2000.
[39] S. Maikap, S. Ray, S. John, S. Banerjee, and C. Maiti, "Electrical characterization of ultra-thin gate oxides on Si/Si1-x-yGexCy/Si quantum well heterostructures," Semiconductor science and technology, vol. 15, p. 761, 2000.
[40] H. Mertens, R. Ritzenthaler, A. Hikavyy, J. Franco, J. W. Lee, D. Brunco, et al., "Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins," in VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, 2014, pp. 1-2.
[41] J. Huang, P. Kirsch, J. Oh, S. Lee, J. Price, P. Majhi, et al., "Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT," in VLSI Technology, 2008 Symposium on, 2008, pp. 82-83.
[42] K. Linder, F. Zhang, J.-S. Rieh, P. Bhattacharya, and D. Houghton, "Reduction of dislocation density in mismatched SiGe/Si using a low-temperature Si buffer layer," Applied physics letters, vol. 70, pp. 3224-3226, 1997.
[43] R. Zhang, N. Taoka, P.-C. Huang, M. Takenaka, and S. Takagi, "1-nm-thick EOT high mobility Ge n-and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 28.3. 1-28.3. 4.
[44] H.-C. Cheng, F.-S. Wang, and C.-Y. Huang, "Effects of NH3 plasma passivation on N-channel polycrystalline silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 44, pp. 64-68, 1997.
[45] M.-W. Ma, T.-S. Chao, T.-Y. Chiang, W.-C. Wu, and T.-F. Lei, "Impacts of N2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-k Gate Dielectric," IEEE Electron Device Letters, vol. 29, pp. 1236-1238, 2008.
[46] C.-C. Li, K.-S. Chang-Liao, L.-T. Chen, C.-H. Fu, H.-Z. Hong, M.-C. Li, et al., "Low inversion equivalent oxide thickness and enhanced mobility in MOSFETs with chlorine plasma interface engineering," Solid-State Electronics, vol. 101, pp. 33-37, 2014.
[47] W.-C. Wu, C.-S. Lai, S.-C. Lee, M.-W. Ma, T.-S. Chao, J.-C. Wang, et al., "Fluorinated HfO2 gate dielectrics engineering for CMOS by pre-and post-CF4 plasma passivation," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[48] M.-W. Ma, T.-Y. Chiang, W.-C. Wu, T.-S. Chao, and T.-F. Lei, "Characteristics of HfO2/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO2 Gate Dielectric and O2 Plasma Surface Treatment," IEEE Transactions on Electron Devices, vol. 55, pp. 3489-3493, 2008.
[49] S. Yamakawa, S. Yabuta, A. Ban, M. Okamoto, M. Katayama, Y. Ishii, et al., "Plasma Treatment Effect on the Off Current Characteristics of a‐Si TFT," in SID Symposium Digest of Technical Papers, 1998, pp. 443-446.
[50] K. C. Moon, J.-H. Lee, and M.-K. Han, "Improvement of polycrystalline silicon thin film transistor using oxygen plasma pretreatment before laser crystallization," IEEE Transactions on Electron Devices, vol. 49, pp. 1319-1322, 2002.