年來，半導體產業的興起帶動了電子產業市場的發展。現代的電子產品被要求多功能、體積小和操作速度快等能力。在此驅動力下，電子產品中的電晶體必須不斷的微縮及高密度以符合電子產業的需求。然而，傳統的電晶體微縮會遇到許多物理極限的挑戰像是導通電流不足夠提升電晶體效能.因此，許多學者提出用高載子遷移率材料來取代原本的矽通道。
在本篇論文中，提出了互補式鍺通道鰭式電晶體在絕緣的矽基板上，能應用在未來次7奈米互補式電晶體技術。利用減壓化學氣象沉積法將厚鍺層成長於矽基板上當作通道來提升載子的遷移率。在完成N型和P型反轉式鍺鰭式電晶體後，利用鋁銅金屬線連接N型和P型集極端來形成鍺的互補式電晶體。在基礎元件特性分析中，第一部分分析N型和P型鍺鰭式電晶體的電性，可以發現N型和P型鍺鰭式電晶體具有較為接近對稱的電特性，適合應用於互補式電晶體電路。第二部分分析互補式鍺通道鰭式電晶體的電性，互補式鍺通道鰭式電晶體具有良好的反轉特性，並且在0.8V工作電壓下可以得到一個較大的電壓增益51.4V/V 。
此篇研究中提出互補式鍺通道鰭式電晶體在絕緣的矽基板上有良好的電特性，因此有機會可以應用在未來次7奈米互補式電晶體技術和三維積體電路上。

Recently, the rise of semiconductor industry is driving the development of electrical industrial market. Modern electronic devices are required to have multifunctional, small size, fast operating speed, etc. Under this driving force, transistors need scaling down continuously and high density to fit the demand for the electronics industry. However, the conventional transistors face a lot of physical challenges such as conductive current not enough to improve transistor performance when they scale down. Therefore, many scholars present using high carrier mobility materials instead of silicon channel.
In this thesis, we successfully demonstrate Germanium complementary metal–oxide–semiconductor(CMOS) on Silicon on Insulator(SOI) substrate. The thick Germanium layer which was deposited on silicon substrate by reduced-pressure chemical vapor deposition (RP-CVD) as channel improve carrier mobility. After n-type and p-type Germanium IM-FinFETs was done, the two drain terminals which are respectively n-type and p-type Germanium IM-FinFETs were connected by AlCu metal lines to from Germanium CMOS. In the basic device characteristics analysis, n-type and p-type Germanium IM-FinFETs on SOI substrate were measured in the first part. The closed symmetrical electrical characteristics indicated that Germanium IM-FinFETs on SOI substrate have potential in CMOS circuits. In the second part, Germanium CMOS on SOI substrate were measured. The results exhibit that Germanium CMOS on SOI substrate have good complementary characteristic and obtain the maximum voltage gain which is 51.4V/V at VDD of 0.8 V.
As a result, we proposed Germanium CMOS on SOI substrate have good electrical characteristics. Additionally, the Germanium CMOS on SOI substrate are highly promising candidate for future sub-7nm CMOS technology and 3D IC applications.

Contents
中文摘要 - II
Abstract - IV
Acknowledge - VI
Contents - VII
Table Contents - VIII
Figure Captions -IX
Chapter 1 - 1
Introduction - 1
1-1 Options beyond Moore's law - 1
1-2 High mobility channel materials - 4
1-3 Germanium FinFET on Silicon On Insulator substrate - 6
1-4 Germanium CMOS inverter on Germanium On Insulator substrate - 10
1-5 High-κ options are used as gate oxide for Germanium CMOS - 14
1-6 Motivation - 16
1-7 Thesis Organization - 17
Chapter 2 - 18
MOSFET Mechanism - 18
2-1 Basic Principle of MOSFET - 18
2-2 MOSFET Parameters Calculation - 20
2-3 Basic Principle of CMOS - 25
Chapter 3 -28
Device Fabrication and Structure -28
3-1 Device Fabrication Process - 28
3-2 SEM image after FIB image of device structure - 31
3-3 Transmission Electron Microscope(TEM) and TEM Energy Dispersive Spectroscopy (EDS) images of device structure - 33
Chapter 4 - 37
Characteristics Analysis - 37
4-1 Characteristics Analysis for Germanium IM-FinFETs on SOI device - 37
4-2 Germanium CMOS Device Analysis - 43
Chapter 5 - 48
Conclusion - 48
Reference - 50
Table Contents
Table 1-1 Lists of electron and hole mobilities, electron and hole effective masses, and bandgap and permittivity for high mobility materials[1-5] - 5
Table 2-1 Physical properties of transistors[2-8] - 24

Figure Captions
Figure 1-1. Transistor counts 1971-2004 & Moore's law - 2
Figure 1-2. IMEC logic device roadmap - 3
Figure 1-3. A variety of CMOS structures using III–V/Germanium channels - 3
Figure 1-4. XRD data for the epitaxial different thickness of Germanium on SOI substrate. Higher Germanium (004) peak indicates 60nm Germanium film has greater crystallinity on SOI substrate[1-6] - 7
Figure 1-5. (a) TEM image of 30nm Germanium film on SOI substrate. High dislocation density exists in Germanium film accompanying with high roughness. (b)TEM image of 60nm Germanium film on SOI substrate. Lower dislocation density with smooth surface is observed. (c) Misfit dislocations release the stress of lattice mismatch at the interface. (d) Lattice image of the single crystalline Germanium film [1-6] - 8
Figure 1-6. ID-VG characteristics of n and p Germanium channel FinFETs on SOI substrate with 50nm fin width and 170nm channel length[1-6] - 9
Figure 1-7. ID-VD characteristics of n and p Germanium channel FinFETs on SOI substrate with 50nm fin width and 170nm channel length[1-6] - 9
Figure 1-8. 3D device structures and key geometry parameters of Germanium nanowire CMOS[1-7] - 11
Figure 1-9. ID-VG characteristics of IM pFinFETs and AM nFinFETs with 40nm fin width and 50nm channel length[1-7] - 11
Figure 1-10. ID-VD characteristics of IM pFinFETs and AM nFinFETs with 40nm fin width and 50nm channel length[1-7] -12
Figure 1-11. VIN-VOUT curves of the Germanium hybrid CMOS on GOI substrate with 40nm fin width and 50nm channel length[1-7] - 12
Figure 1-12. VIN-VOUT curves of the Germanium hybrid CMOS on GOI substrate with 40nm fin width and 100nm channel length, the maximum gain is 54 V/V at a low VDD of 1 V[1-7] - 13
Figure 1-13. Cross-sectional TEM images of Al2O3/GeO2/Germanium interfaces in the MOSFETs [1-8] - 15
Figure 1-14. Energy distribution of Dit in Al2O3/GeO2/Germanium p-MOSFETs and GeO2/Germanium MOS capacitors [1-8] - 15
Figure 2-1. Basic structure of N-type MOSFET[2-5] - 19
Figure 2-2. The band bending of the P-type substrate[2-5] - 19
Figure 2-3. Extracted threshold voltage by constant current method[2-6] - 23
Figure 2-4. DIBL is shown in n-channel MOSFET[2-7] - 23
Figure 2-5. (a) CMOS inverter with Vdd = 2 V and Vss = 0V; (b) Idd vs. Vds curve of p-type and n-type MOSFETs and (c) Vout = VdsN = 2 V + VdsP according to (a) [2-9] - 26
Figure 2-6. The VTC of a CMOS inverter[2-9] - 27
Figure 3-1. Scheme of Germanium CMOS structure on SOI substrate - 30
Figure 3-2. The detail process flow of Germanium CMOS on SOI substrate and the cross section of schematic along the gate direction - 30
Figure 3-3. (a)-(b) Cross-section of the channel structures for Germanium CMOS on SOI substrate. A and A’ indicate gate cross-section image - 31
Figure 3-4. (a)presents the cross section of Germanium CMOS on SOI substrate; (b) and (c)show the cross-section Focused Ion Beam(FIB) image for Germanium CMOS on SOI substrate with different fin widths after dry etch gate area - 32

Figure 3-5. (a) Cross-sectional TEM image of Germanium CMOS on SOI substrate along A-A' ;(b) and (c) are enlarged gate oxide view of (a) with left gate oxide is 2.16 nm and right gate oxide is 1.39 nm - 34
Figure 3-6. Cross-sectional EDS-mapping images on the TEM of Germanium CMOS on SOI substrate. All the elements correspond their mapping colors in EDS-mapping images - 35
Figure 3-7. Cross-sectional EDS-spot images on the TEM of Germanium CMOS on SOI substrate. All the elements correspond their peaks in EDS-spot images - 36
Figure 4-1. ID-VG curves of the n-type and p-type Germanium IM-FinFETs on SOI substrate with 35nm fin width and 70nm channel length - 38
Figure 4-2. The value of ON/OFF ratio, VTH, SSmin and DIBL with 35nm fin width and 70nm channel length n-type and p-type Germanium IM-FinFETs on SOI substrate at VD=0.1 - 38
Figure 4-3. ID-VD curves for (a)n-type Germanium IM-FinFET on SOI substrate and (b)p-type Germanium IM-FinFET on SOI substrate with 35nm fin width and 70nm channel length - 39
Figure 4-4. ID-VG curves of the n-type and p-type Germanium IM-FinFETs on SOI substrate with 50nm fin width and 80nm channel length - 40
Figure 4-5. The value of ON/OFF ratio, VTH, SSmin and DIBL with 50nm fin width and 80nm channel length n-type and p-type Germanium IM-FinFETs on SOI substrate at VD=0.1 - 41
Figure 4-6. ID-VD curves for (a)n-type Germanium IM-FinFET on SOI substrate and (b)p-type Germanium IM-FinFET on SOI substrate with 50nm fin width and 80nm channel length - 42
Figure 4-7. (a)The schematic of Germanium CMOS on SOI substrate mask and (b)the optical microscope(OM) image of Germanium CMOS on SOI devices - 44
Figure 4-8. (a)The voltage transfer current(VTC) of Germanium CMOS on SOI substrate with 35nm fin width and 70nm channel length and (b)Vin vs. Voltage gain which was extracted from (a) - 46
Figure 4-9. (a)The voltage transfer current(VTC) of Germanium CMOS on SOI substrate with 40nm fin width and 60nm channel length and (b)Vin vs. Voltage gain which was extracted from (a) - 47

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