|
[1] S. Zhai et al., “The Requirement Analysis of 400GE FEC for Gen1 PMDs,” IEEE 400Gb/s Ethernet Study Group, July 2013. [Online]. Available: http://www.ieee802.org/3/400GSG/public/13_07/zhai_400_01_0713.pdf [2] X. Song and D. Dove “Opportunities for PAM4 modulation” Huawei Technologies. [3] J. Kim, Buckwalter, J.F. , "A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS," IEEE J. of Solid-State Circuits, vol.47, no.3, pp.615–626, March 2012. [4] S. Nakano, M. Nogawa, H. Nosaka, A. Tsuchiya, H. Onodera and S. Kimura, "A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking," Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian, Xiamen, 2015 [5] Sung Min Park and Hoi-Jun Yoo, "1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications," IEEE Journal of Solid-State Circuits, vol. 39, no.1, pp. 112-121, Jan. 2004. [6] C. Lee, L. c. Cho and S. i. Liu, "A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology," 2005 IEEE Asian Solid-State Circuits Conference, Hsinchu, 2005, pp. 129-132. [7] M. S. Kao, F. T. Chen, Y. H. Hsu and J. M. Wu, "20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 475-483, March 2014. [8] Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang and Yang-Tung Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp.1158-1169, May 2011. [9] Wei-Zen Chen and Da-Shin Lin, “A 90-dB 10-Gb/s optical receiver analog front-end in a 0.18-um CMOS technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 15, no. 3, pp. 358–365, Mar. 2007. [10] Wei-Zen Chen, Ying-Lien Cheng and Da-Shin Lin, “ A 1.8V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-End,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1388-1396, Jun. 2005. [11] Chao-Yung Wang, Chao-Shiun Wang, and Chorng-Kuang Wang, "An 18-mW two-stage CMOS transimpedance amplifier for 10 Gb/s optical application." Solid-State Circuits Conference (A-SSCC), 2007. [12] Chih-Fan Liao and Shen-Iuan Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J.Solid-State Circuits, vol. 43, no. 3, pp. 642–655, Mar. 2008. [13] Samira Bashiri, Calvin Plett, Jorge Aguirre and Peter Schvan,“A 40Gb/s Transimpedance Amplifier in 65nm CMOS Technology,” in Proc. IEEE Int. Symp. on Circuits and Systems, 2010, pp. 757 –760. [14] Joohwa Kim and Buckwalter, J.F, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 1-4, March 2012. [15] J. Kim and James F. Buckwalter, “Bandwidth enhancement with low groupdelay variation for a 40-Gb/s transimpedance amplifier,” IEEE Trans.Circuits Syst. I: Reg. Papers, vol. 57, no. 8, pp. 1964–1972, Aug. 2010. [16] Shekhar, Sudip, Jeffrey S. Walling, and David J. Allstot, "Bandwidth extension techniques for CMOS amplifiers," IEEE Journal of Solid-State Circuits, vol 41, no.11, pp. 2424-2439, Nov.2006. [17] Christian Kromer, Gion Sialm, Christoph Berger, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni, Gian-Luca Bona and Heinz Jäckel, “A 100mW 4x10 Gb/s transceiver in 80 nm CMOS for high-density optical interconnects,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2667–2679, Dec. 2005. [18] Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen and Shen-Iuan Liu, "CMOS wideband amplifiers using multiple inductive-series peaking technique," IEEE J.Solid-State Circuits, vol. 40, no. 2, pp. 548-552, Feb. 2005. [19] D. Li et al., "A Low-Noise Design Technique for High-Speed CMOS Optical Receivers," IEEE J.Solid-State Circuits, vol. 49, no. 6, pp. 1437-1447, June 2014. [20] Mohamed Atef and Horst Zimmermann, "Optical receiver using noise cancelling with an integrated photodiode in 40 nm CMOS technology." Circuits and Systems I: Regular Papers, IEEE Transactions on, 2013, pp. 1929-1936. [21] Shun-Tien Chou, Shih-Hao Huang, Zheng-Hao Hong and Wei-Zen Chen, "A 40 Gbps optical receiver analog front-end in 65 nm CMOS." Circuits and Systems (ISCAS), 2012 IEEE International Symposium on. IEEE, 2012. [22] Ahmed, Muhammad Najebul, Johanna Chong, and Dong Sam Ha, "A 100 Gb/s transimpedance amplifier in 65 nm CMOS technology for optical communications." Circuits and Systems (ISCAS), IEEE, 2014. [23] Szilagyi, Laszlo, Ronny Henker, and Frank Ellinger, "An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency," International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE, 2014. [24] M.H. Taghavi, L. Belostotski, and J. W. Haslett, "A bandwidth enhancement technique for CMOS TIAs driven by large photodiodes." New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International. IEEE, 2012. [25] Cheng Li and Samuel Palermo, ”A low-power 26-GHz transformer based regulated cascode SiGe BiCMOS transimpedance amplifier,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp.1264-1275, May. 2013. [26] Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo A. Aroca, Peter Schvan, Ming-Ta Yang and Sorin P. Voinigescu, "Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS," IEEE Journal of Solid-State Circuits, vol.42, no.7, pp.1564-1573, July.2007. [27] S. G. Kim et al., "A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology," IEEE A-SSCC, KaoHsiung, 2014, pp. 357-360. [28] 陳聖文, “應用於光連結系統之高速前端電路與光電介面交換機設計,”國立清華大學電子工程研究所碩士論文,2012。 [29] 邱柏崴, “光連結系統之高速收發機電路與交換機設計及量測,”國立清華大學電子工程研究所碩士論文,2013。 [30] 劉彥廷, “超高速光通訊前端電路設計,”國立清華大學電子工程研究所碩士論文,2014。 [31] 廖景輝, “高速光通訊前端類比電路設計,”國立清華大學電子工程研究所碩士論文,2015。 [32] 王柏鈞, “高速光通訊傳輸端電路設計,”國立清華大學電子工程研究所碩士論文,2015。 [33] 李彥鋒, “高速光通訊前端電路設計宇收發元件等效電路建立,”國立清華大學電子工程研究所碩士論文,2016。
|