帳號:guest(18.218.190.237)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):余易弦
作者(外文):Yu, I-Hsien
論文名稱(中文):利用Digital Etch改善準垂直型溝槽式閘極氮化鎵金氧半場效電晶體特性之研究
論文名稱(外文):Investigation on Characteristics of Quasi-Vertical Trench Gate GaN MOSFET Treated with Digital Etch
指導教授(中文):黃智方
指導教授(外文):Huang, Chih-Fang
口試委員(中文):龔正
吳添立
口試委員(外文):Gong, Jeng
Wu, Tian-Li
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:103063544
出版年(民國):106
畢業學年度:105
語文別:中文
論文頁數:69
中文關鍵詞:氮化鎵準垂直金氧半場效電晶體
外文關鍵詞:GaNQuasi-VerticalMOSFET
相關次數:
  • 推薦推薦:0
  • 點閱點閱:525
  • 評分評分:*****
  • 下載下載:21
  • 收藏收藏:0
本篇論文主要在研製準垂直型溝槽式氮化鎵金氧半場效電晶體於藍寶石基板。藉由高解析度X光電子能譜分析,可以發現經由感應式耦合電漿蝕刻後會使得Ga 2p3/2元素訊號的峰值位移,指出其材料表面遭受破壞,為了解決表面破壞的情形,本論文採取Digital Etch(D.E)的蝕刻方式進行表面處理,且探討晶面及D.E表面處理對元件特性的影響。
本論文採用不同表面處理方式,分別為:(a)浸泡鹽酸、BOE與硫酸,(b)在200oC環境下進行10次的D.E,(c)在200oC環境下進行20次的D.E,(d)在200oC環境下進行20次的D.E搭配浸泡酸液,及(e)在450oC環境下進行20 次的D.E搭配浸泡酸液。
由量測結果得知,即使經過不同條件的表面處理,蝕刻過後的溝槽表面仍存在許多的陷阱,必須使用脈衝模式及搭配UV光照射的量測方式,才可以得到合理的輸出特性,整體而言,元件在200oC環境下進行20次的D.E表面處理過後可得到最佳的元件特性,該臨界電壓為5.5 V、最大汲極電流密度達0.83 A/mm2,經計算後的場效遷移率僅有4.8 (cm2/V-s)。
In this study, quasi-vertical trench gate of the gallium nitride (GaN) MOSFETs were fabricated on sapphire substrate. From high-resolution X-ray photoelectron spectroscopy (HR-XPS) analysis, it was found that the Ga 2p3/2 peak was shifted by the etching of inductive coupling plasma, which indicates that the surface was damaged. In order to recover the surface properties, the treatment of digital etch (D.E) on the surface was carried out.
Five samples with quasi-vertical MOSFETs going through different surface treatments listed as the following were completed and compared: (a) soaking in hydrochloric acid, BOE and sulfuric acid. (b) 10 cycles of D.E at 200 °C (c) D.E for 20 cycles in a 200 °C environment. (d) 20 cycles of D.E at 200 °C with soaking in acids. (e) 20 cycles of D.E at 450 °C with soaking in acids.
From the measurements, it was discovered that even though the surface had been through different treatments, there might still exist a lot of traps on the etched trench surface. Pulse mode must be used in measurements together with UV light on in order to obtain reasonable output characteristics. Overall, the device treated with 20 cycles of digital etch at 200 ° C has the best device characteristics. With a threshold voltage (Vth) of 5.5 V and a maximum drain current density of 0.83 A/mm2, the calculated mobility is only 4.8 (cm2/V-s).
中文摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 前言 1
1.2 研究動機與文獻回顧 3
1.3 研究方向簡介與論文架構 10
1.3.1 研究方向簡介 10
1.3.2 論文架構 10
第二章 材料介紹與實驗設計 11
2.1 氮化鎵材料介紹與基板選擇 11
2.2 試片磊晶結構 12
2.3 閘極氧化層 14
2.4 Digital Etch 14
2.5 元件設計 15
2.6 試片分類 18
第三章 光罩設計與元件製程 19
3.1 準垂直型溝槽式閘極金氧半場效電晶體製作流程 19
3.2 試片溶劑清潔 20
3.3 溝槽式閘極及對準記號蝕刻 (Mask 1) 20
3.4 基極溝槽蝕刻(Mask 2) 22
3.5 汲極深蝕刻(Mask 3) 24
3.6 表面處理與閘極氧化層 25
3.7 源極電極之製作 (Mask 4) 26
3.8 基極電極之製作 (Mask 5) 28
3.9 閘極金屬與源極襯墊金屬之製作 (Mask 6) 29
3.10 汲極電極之製作 (Mask 7) 30
第四章 元件量測結果分析 31
4.1 歐姆接觸量測 31
4.2 電容量測 34
4.3 閘極氧化層耐壓特性 37
4.4 Digital Etch實驗分析 39
4.5 元件正向電性量測 46
4.5.1 直流DC模式下之電性量測 46
4.5.2 直流DC模式下照射UV之電性量測 46
4.5.3 脈衝(Pulse)模式下照射UV之電性量測 47
4.6 升溫量測 58
4.7 通道於不同晶向探討 63
第五章 結論與未來工作 64
參考文獻 65
[1] N. Kaminski, “State of the art and the future of wide band-gap devices,” in Proc. IEEE Power Electron. Appl. pp. 1-9, 2009.
[2] M. N. Yoder, “Wide bandgap semiconductor materials and devices,” IEEE Trans. Electron Devices, vol. 43, pp. 1633-1636, 1996.
[3] R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W. L. Pribble, “A review of GaN on SiC high electron-mobility power transistors and MMICs,” IEEE Trans. Microwave Theory and Techniques, vol. 60, no. 6, pp. 1764–1783, Jun. 2012.
[4] B. J. Baliga, “Advanced Power MOSFET Concepts,” Springer Verlag, 2010.
[5] S. Liu, S. Yang, Z. Tang, Q. Jiang, C. Liu, M. Wang, and Kevin J. Chen, “Al2O3/AlN/GaN MOS-channel-HEMTs with an AlN interfacial layer,” IEEE Electron Device Lett., vol. 35, no. 7, pp. 723-725, Jul. 2014.
[6] C. L. Hinkle, M. Milojevic, B. Brennan, A. M. Sonnet, F. S. Aguirre-Tostado, G. J. Hughes, E. M. Vogel, and R. M. Wallace, “Detection of Ga suboxides and their impact on III–V passivation and Fermi-level pinning,” Appl. Phys. Lett., vol. 94, no. 16, pp. 162101-1–162101-3, Apr. 2009.
[7] S. Ozaki, T. Ohki, M. Kanamura, T. Imada, N. Nakamura, N. Okamoto, T. Miyajima, and T. Kikkawa, “Effect of oxidant source on threshold voltage shift of AlGaN/GaN MIS-HEMTs using ALD-Al2O3 gate insulator films,” in Proc. CS MANTECH Conf., Apr. 2012, pp. 1–4.
[8] M. Kanechika, M. Sugimoto, N. Soejima, H. Ueda, O. Ishiguro, M. Kodama, E. Hayashi, K. Itoh, T. Uesugi, and T. Kachi, “A vertical insulated gate AlGaN/GaN heterojunction field-effect transistor,” Jpn. J. Appl. Phys., vol. 46, pp. L503–505, 2007.
[9] H. Otake, S. Egami, H. Ohta, Y. Nanishi, and H. Takasu, “GaN-based trench gate metal oxide semiconductor field effect transistors with over 100 cm2/(V·s) channel mobility,” Jpn. J. Appl. Phys., vol. 46, pp. L599–L601, 2007.
[10] H. Otake, K. Chikamatsu, A. Yamaguchi, T. Fujishima, and H. Ohta, “Vertical GaN-based trench gate metal oxide semiconductor field-effect transistors on GaN bulk substrates,” Appl. Phys. Exp., vol. 1, no. 1,art. no. 011105, pp. 1-3, 2008.
[11] C. H. Won, K. W. Kim, D. S. Kim, H. S. Kang, K. S. Im, Y. W. Jo, D. K. Kim, R. H. Kim, and J. H.Lee, “Normally-off vertical-type mesa-gate GaN MOSFET,” IET Electron. Lett., vol. 50, no. 23, pp. 1749-1751, 2014.
[12] H. Nie, Q. Diduck, B. Alvarez, A. P. Edwards, B. M. Kayes, M. Zhang, G. Ye, T. Prunty, D. Bour, and I. C. Kizilyalli, “1.5-kV and 2.2-mΩ-cm2 vertical GaN transistors on bulk-GaN substrates,” IEEE Electron Device Lett., vol. 35, no. 9, pp. 939-941, Sept. 2014.
[13] T. Oka, Y. Ueno, T. Ina, and K. Hasegawa, “Vertical GaN-based trench metal oxide semiconductor field–effect transistors on a freestanding GaN substrate with blocking voltage of 1.6 kV,” Appl. Phys. Exp., vol. 7, no. 2, art. no. 021002, pp. 1-3, 2014.
[14] R. Li, Y. Cao, M. Chen, R. Chu, “600 V/1.7  Normally-off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor,” IEEE Electron Device Lett., vol. 37, no. 11, pp. 1466-1469, Nov. 2016.
[15] M. Kodama, M. Sugimoto, E. Hayashi, N. Soejima, O. Ishiguro, M. Kanechika, K. Itoh, H. Ueda, T. Uesugi, T. Kachi, “GaN-based trench gate metal oxide semiconductor field-effect transistor fabricated with novel wet etching,“ Appl. Phys. Exp., vol. 1, no. 2, pp. 021104, Feb. 2008.
[16] K. W. Kim, S. D. Jung, D. S. Kim, H. S. Kang, K. S. Im, J. J. Oh, J. B. Ha, J. K. Shin, and J. H. Lee, “Effect of TMAH treatment on device performance of normally off Al2O3/GaN MOSFET,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1376-1378, Oct. 2011.
[17] J. Lin, X. Zhao, D. A. Antoniadis, and J. A. del Alamo, “A novel digital etch technique for deeply scaled III–V MOSFETs,” IEEE Electron Device Lett., vol. 35, no. 4, pp. 440–442, Apr. 2014.
[18] A. Alian, C. Merckling, G. Brammertz, M. Meuris, M. Heyns, and K. D. Meyer, “InGaAs MOS transistors fabricated through a digital-etch gate-recess process and the influence of forming gas anneal on their electrical behavior,” ECS J. Solid State Sci. Tech nol., vol. 1, no. 6, pp. 310–314, 2012.
[19] X. Zhao and J. A. del Alamo, “Nanometer-scale vertical-sidewall reactive ion etching of InGaAs for 3-D III-V MOSFETs,” IEEE Electron Device Lett., vol. 35, no. 5, pp. 521–523, May 2014.
[20] D. Buttari, S. Heikman, S. Keller, and U. K. Mishra, “Digital etching for highly reproducible low damage gate recessing on AlGaN/GaN HEMTs,” in Proc. IEEE Lester Eastman Conf. High Perform. Devices, pp. 461–469, Aug. 2002
[21] S. D. Burnham, K. Boutros, P. Hashimoto, C. Butler, D. W. S. Wong, M. Hu, and M. Micovic, “Gate recessed normally off GaN on Si HEMT using a new O2BCl3 digital etching technique,” Phys. Stat. Sol. (C), vol. 7, no. 7/8, pp. 2010–2012, Jul. 2010.
[22] D. Keogh, P. Asbeck, T. Chung, R. D. Dupuis, and M. Feng, “Digital etching of III-N materials using a two-step Ar/KOH technique,” J. Electron. Mater., vol. 35, no. 4, pp. 771–776, Apr. 2005.
[23] K. Tadatomo, H. Okagawa, Y. Ohuchi, T. Tsunekawa, Y. Imada, M. Kato, and T. Taguchi, “High output power InGaN ultraviolet light emitting diodes fabricated on patterned substrates using metalorganic vapor phase epitaxy,” Jpn. J. Appl. Phys., vol. 40, pp. L583–L585, 2001.
[24] N. Shiozaki, T. Sato, and T. Hashizume, “Formation of thin native oxide layer on n-GaN by electrochemical process in mixed solution with Glycol and Water,” Jpn. J. Appl. Phys., vol. 46, no. 4A, pp. 1471–1473, 2007.
[25] Y. J. Lin, Q. Ker, C. Y. Ho, H. C. Chang, and F. T. Chien, ”Nitrogen-vacancy-related defects and Fermi level pinning in n-GaN Schottky diodes,” J. Appl. Phys., vol. 94, pp. 1819, 2003.
[26] D. Selvanathan, F. M. Mohammed, J. O. Bae, I. Adesida, and Katherine H. A. Bogart, “Investigation of surface treatment sscheme on n-type GaN and Al0.20Ga0.80N,” J. Vac. Sci. Technol. B, vol. 23, pp. 2538, 2005.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *