近年來一種全新的無線收發機架構被提出來稱之為“全雙工無線收發機” (Full Duplex Radio, FDR)，此種架構之射頻收發機使用著同樣的發射時間與頻率，理論上全雙工無線收發機架構之射頻收發機能達到相對於傳統分頻雙工(Frequency Division Duplex, FDD)或是分時雙工(Time Division Duplex, TDD)收發機兩倍之訊號處理能力。全雙工無線收發機架構主要的挑戰為發射機所輸出訊號會漏往接收機端而導致自我干擾(Self-interference)。因此，使用類比射頻電路降低收發機之self-interference為本研究所著重之開發重點。
為了達到降低收發機之self-interference而使用相移器與衰減器，並在晶片的設計中提出使用3-D電感，大幅縮小晶片面積。在第一章中，將介紹全雙工無線收發機架構與目前全雙工無線收發機所遇到之困難。在第二章中，討論3-D電感的設計，並自行設計正八邊形symmetric 3-D電感以及比較Sonnet與HFSS兩套模擬軟體對相同電感的模擬差異。第三章中，反射式負載相移器電路以TSMC-90nm CMOS製程實現設計電路，其核心面積僅有0.119 mm2，為目前操作在同頻率所發表的論文中最小之反射式負載相移器電路，且根據量測結果，此電路在5.8 GHz時具有360度的相位移效果，而在5.6至6.2 GHz的範圍時，輸入/輸出反射損耗(Return Loss)均在10dB以上，插入損耗(Insertion Loss)則介於6.1至16.7 dB之間。第四章中，同樣使用90-nm CMOS製程實現設計之類比開關調控相移器，模擬數據顯示，當類比調控相移器晶片操作頻率在5.8 GHz時，輸入/輸出反射損耗(Return Loss)達7 dB以上，插入損耗(Insertion Loss)則介於4至20 dB之間，相位變化達360度以上，而核心電路面積僅有0.26 mm2。第五章中，亦使用90-nm CMOS製程實現設計之T-type衰減器晶片，模擬顯示最大衰減量可達到31.4 dB，但由於ESD PAD無法使用負電壓進行操作，導致量測之衰減量範圍較模擬小，衰減範圍由1.8 dB衰減至18.7 dB。根據量測結果，當電路操作頻率介於5.6至6.2 GHz時，輸入與輸出的反射係數皆大於15 dB，最大相位變化約為35度。

A new type of transceiver which called “Full Duplex Radio” (FDR) has been proposed in recent years. Theoretically, the FDR architecture allows to transmit and receive the signal simultaneously at the same frequency, which can achieve double of wireless signal capacity than the traditional FDD (Frequency Division Duplex) and TDD (Time Division Duplex) design. The main challenge of FDR architecture is the leakage of transmitted signal from the transceiver to the receiver, resulting in self-interference. This study focuses on reduction of the self-interference of the transceiver using RF analog circuits.
The phase shifter and attenuator are employed to reduce the self-interference of transceiver. In order to reduce the chip size, the 3-D inductors are utilized intensively in our designs. In chapter 1, we will introduce the FDR system architecture and the difficulty of FDR system development. In chapter 2, we discuss the 3-D inductors design, propose an octagonal symmetric 3-D inductor and compare the simulated results by Sonnet with that by HFSS. In chapter 3, the reflection-type phase shifter is designed by the tsmc-90nm CMOS technology. The core area is only about 0.119 mm2, which is among the smallest compared with other published reflection-type phase shifters with a similar operating frequency. The measured phase tuning range achieves 360 degrees at 5.8 GHz, and the input/output return losses from 5.6 to 6.2 GHz are more than 10 dB and the insertion loss ranges from 6.1 to 16.7 dB. In chapter 4, the analog tunable switch-type phase shifter is proposed and demonstrated also in 90-nm CMOS. The simulated input/output return losses are more than 7 dB, insertion loss is from 4 to 20 dB and phase tuning range is more than 360 degrees at 5.8 GHz. The core area is only about 0.26 mm2. In chapter 5, a 6-bit T-type attenuator is demonstrated in 90-nm CMOS. The simulated results indicate that a maximum attenuation can achieve 31.4 dB. However, the measured results show a relatively small attenuation range from 1.8 to 18.7 dB, which is because the negative control voltage cannot be used by ESD PAD design. According to the measurement results, the input/output return loss are more than 15 dB, and the maximum phase difference is about 35 degree when frequency is from 5.6 to 6.2 GHz.

第1章 緒論 11
1.1 研究背景與動機 11
1.2 論文架構 13
第2章 3-D電感設計與模擬比較 14
2.1 STACKED INDUCTOR 15
2.2 SOLENOID INDUCTOR 17
2.3 SYMMETRIC INDUCTOR 18
2.4 圖樣化屏蔽接地(PATTERN GROUND SHIELDING, PGS) 19
2.5 3-D電感模擬與比較 20
2.5.1 Symmetric 3-D電感模擬與比較 20
2.5.2 模擬軟體sonnet與HFSS模擬結果比較 23
2.6 本章總結 25
第3章 反射式負載之相移器設計 26
3.1 研究動機 28
3.2 反射式負載相移器設計 29
3.3 模擬與量測 32
3.3.1 3dB-90o耦合器模擬 32
3.3.2 反射式負載端之3-D電感模擬 35
3.3.3 反射式負載相移器模擬與量測 36
3.4 本章總結 39
第4章 類比開關調控相移器設計 42
4.1 研究動機 42
4.2 類比開關調控相移器設計 43
4.2.1 類比開關調控相移器之3-D電感設計 48
4.3 電路模擬 50
4.4 本章總結 52
第5章 6-BIT T-TYPE衰減器設計 55
5.1 研究動機 55
5.2 T-TYPE ATTENUATOR設計架構簡介 57
5.2.1 衰減電路使用之電感設計與模擬 61
5.3 模擬與量測 64
5.3.1 電路模擬 64
5.3.2 電路量測 66
5.4 本章總結 70
第6章 結論 73
6.1 總結 73
6.2 未來工作 74
參考文獻 76

[1] D. Bharadia et al, “Full duplex radios”, in Proc. of ACM SIGCOMM, pp. 375-386, 2013.
[2] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology, ” IEEE J. Solid-State Circuits, vol. 36, pp. 620-628, Apr. 2001.
[3] C. -C. Tang, C. -H. Wu, and S. -I. Liu, “Miniature 3-D inductors in standard CMOS process, ” IEEE J. Solid-State Circuits, vol. 37, pp. 471-480, Apr. 2002.
[4] W. -Z. Chen and W. -H. Chen, “Symmetric 3D passive components for RF ICs application,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003, pp. 599-602.
[5] K. J. Koh and G. M. Rebeiz, “0.13-um CMOS phase shifters for X-, Ku-, and K-band phased arrays,” IEEE J. Solid-State Circuit, vol. 42, no. 11, pp. 2535-2546, Nov. 2007.
[6] H. Zarei, C. T. Charles and D. J. Allstot, “Reflective-type phase shifters for multiple-antenna transceivers,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 54, no. 8, pp. 1647-1656, Aug. 2007.
[7] F. Ellinger, R.Vogt and W. Bächtold, “Compact reflective-type phase-shifter MMIC for C-band using a lumped-element coupler,” IEEE Trans. Microw. Theory Techn., vol. 49, pp. 913–917, May. 2001.
[8] F. Ellinger, R. Vogt and W. Bächtold, “Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining,” IEEE J. Solid-State Circuit, vol. 37, no. 4, pp. 481-486, Feb. 2002.
[9] H. Zarei, C. T. Charles and D. J. Allstot, “Reflective-type phase shifters for multiple-antenna transceivers,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 54, no. 8, pp. 1647-1656, Aug. 2007.
[10] W. -T. Li, J. -H. Tsai, M. Huang and T. -W. Huang, “A 3.5–4.5-GHz ultra-compact 0.25mm2 reflection-type 360° phase shifter,” 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore, MD, 2011, pp. 1-4.
[11] H. Zarei and D. J. Allstot, “A low-loss phase shifter in 180nm CMOS for multiple-antenna receivers,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004.
[12] M. Meghdadi, M. Azizi, M. Kiani, A. Medi and M. Atarodi, “A 6-bit CMOS phase shifter for S -band, ” in IEEE Trans. Microw. Theory and Techn., vol. 58, no. 12, pp. 3519-3526, Dec. 2010.
[13] W. -T. Li, Y. -C. Chiang, J. -H. Tsai, H. -Y. Yang, J. -H. Cheng and T. -W. Huang, “60-GHz 5-bit phase shifter with integrated VGA phase-error compensation, ” in IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1224-1235, March 2013.
[14] R. Amirkhanzadeh, H. Sjöland, J. M. Redouté, D. Nobbe and M. Faulkner, “High-resolution passive phase shifters for adaptive duplexing applications in SOS process, ” in IEEE Trans. Microw. Theory Techn., vol. 62, no. 8, pp. 1678-1685, Aug. 2014.
[15] J. Bae and C. Nguyen, “A novel concurrent 22–29/57–64-GHz dual-band CMOS step attenuator with low phase variations, ” in IEEE Trans. Microw. Theory and Techn., vol. 64, no. 6, pp. 1867-1875, June 2016.
[16] B. W. Min and G. M. Rebeiz, “A 10–50-GHz CMOS distributed step attenuator with low loss and low phase imbalance, ” in IEEE Journal of Solid-State Circuits, vol. 42, no. 11, pp. 2547-2554, Nov. 2007.
[17] S. Sim, L. Jeon and J. G. Kim, “A compact X-band bi-directional phased-array T/R chipset in 0.13um CMOS technology, ” in IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 562-569, Jan. 2013.
[18] J. Bae, J. Lee and C. Nguyen, “A 10–67-GHz CMOS dual-function switching attenuator with improved flatness and large attenuation range, ” in IEEE Trans. Microw. Theory and Techn., vol. 61, no. 12, pp. 4118-4129, Dec. 2013.