FinFET 如今已成為 20 奈米以下半導體製程技術中最主要的元件結構。然而由於 FinFET 的立體的結構性以及線寬的持續變窄，寄生電容與電阻比平面的電晶體更為顯 著。在這篇論文中，我們發展出了一套能夠準確模擬這些寄生電容與電阻對於電晶體以及邏輯閘效能影響的方法。
首先，我們發展出一個電腦程式:以真實的 FinFET 結構為基礎，再加上電路佈 局，建立起準確的 3D 電晶體連結模型。然後我們使用電場模擬器 Raphael，準確的計算出寄生的電容與電阻。3D 電場特有的邊緣場效 (fringing e ect) 以及電流擁擠效應 (current crowding)，也都包含其中。雖然此流程比較費時，但是能夠最準確的模擬出寄生的電容與電阻。
有了準確的寄生電容與電阻的模擬流程，我們進行一系列實驗，觀察各種結構的參 數對寄生電容和電阻的影響，其中包含 n 的高度，MD 的間距等等，並藉此找出每個參數對於電晶體或者邏輯閘的寄生電阻與電容的敏感度的影響。
為進一步了解這些寄生電容與電阻對電路的影響，我們選擇最基本的三種數位閘來研究:正反器 (inverter)，反及閘 (NAND) 以及反或閘 (NOR)。從數位閘的佈局精確 的模擬出寄生電容與電阻的大小，然後使用電路模擬程式 (HSPICE) 以分析對電路的 影響。我們發現閘極 (gate) 和汲極 (drain) 之間的電容以及源極端 (source) 的電阻尤其 關鍵。另外，當閘極的負載相對小的時候，寄生電容的影響較電阻大;反之，當閘極 的附載較大時，寄生電阻的影響則較大。
由於此一程式使用精確的 FinFET 結構以模擬寄生元件，在製程開發前期可以用來 計算寄生元件的數值，以提供為製定設計規則 (design rule) 的參考;而它又接受真實 的電路佈局，更可以當成數位資料庫 (standard cell library) 佈局優化的工具，以增加 新一代半導體製程的競爭性。

For sub-20nm semiconductor technologies, FinFET has evolved to be the main transistor. Due to its 3-D structure and the small line width, parasitics are more significant than planar transistors. In this thesis, we develop an accurate simulation methodology to estimate the impacts of the parasitics to transistor as well as basic digital gate performance.
A program is first written that takes realistic FinFET structure and layout information to build a 3-D representation of the transistor and/or logic gate. Then, a field solver, Raphael, is invoked to simulate parasitic capacitance and resistance accurately. Fringing E-fieeld in capacitance simulation and current crowding in resistance simulation are all taken care with the best accuracy possible.
A series studies are first performed to see various structure parameters, such as fin height, poly-to-MD spacing, impacts to the parasitic capacitance and resistance. Parasitic sensitivities for a single transistor as well as for a logic gate are analyzed.
With the parasitic accurately simulated, circuit simulations are then performed to observe the impacts of these parasitic to circuit performance. Three basic logic gates are investigated: inverter, 2-input NAND gate and 2-input NOR gate. It was found that Cgd (gate to drain capacitance) has the largest impacts among all capacitance components: while source resistor has the largest impact among all di erent parasitic resistors. In addition, when the gate loading is relatively small, parasitic capacitance tends to have larger impact than parasitic resistance. But for large drive gate, where large current is needed, parasitic resistance can plan a very significant role.
Since the impact analysis takes layout information to simulate the circuit performance, this methodology can be very helpful for early stage technology development for design rule analysis. In addition, it is also possible to use it for fundamental gate layout optimization to further increase the competitiveness of the technology in standard cell development.

1 Introduction 1
1.1 Background................................... 1
1.2 ParasiticCapacitanceandResistance..................... 2
1.3 ThesisOrganization .............................. 3

2 GSDII to Raphael Parser 4
2.1 Introduction................................... 4
2.2 GDS file structure ............................... 5
2.3 Cell Flattening ................................. 8
2.4 Pins....................................... 9
2.5 Logic Operations ................................ 11
2.5.1 Dummy Definition ........................... 11
2.5.2 Cut Definition ............................. 13
2.5.3 Channel Definition........................... 14
2.5.4 High LowPoly/MD Differentiation.................. 15
2.6 Signal Propagation ............................... 16
2.7 Parser Output for Raphael Simulations.................... 17
2.8 Generating Capacitance or Resistance Raphael Simulations . . . . . . . . . 19
2.9 User’s Guide for the GDSII to Raphael Parser . . . . . . . . . . . . . . . . 20
2.10 Summary .................................... 22

3 Impacts of Parasitic Capacitance 25
3.1 Introduction................................... 25
3.2 Raphael Simulation Accuracy ......................... 26
3.3 Small Structure................................. 27
3.3.1 Fin height................................ 30
3.3.2 Poly height ............................... 30
3.3.3 High poly height ............................ 33
3.3.4 Low poly height ............................ 35
3.3.5 MD height ............................... 36
3.3.6 Poly to MD spacing .......................... 37
3.3.7 Fin Pitch ................................ 37
3.3.8 Critical Parameters of small structure . . . . . . . . . . . . . . . . 39
3.4 Parameter Impacts on INV Capacitance ................... 40
3.4.1 Fin height................................ 41
3.4.2 Poly height ............................... 41
3.4.3 High poly height ............................ 43
3.4.4 Low poly height ............................ 45
3.4.5 MD height ............................... 45
3.4.6 MD to POSpacing........................... 46
3.4.7 Critical parameters of INV Cgd.................... 48
3.5 Comparing Small Structure and INV Parasitic Capacitance . . . . . . . . . 48
3.6 Comparisons of small structure, INV, ND2 and NR2 . . . . . . . . . . . . 51
3.7 Summary .................................... 53

4 Impacts of Parasitic Resistance 55
4.1 Introduction................................... 55
4.2 Raphael Simulation Accuracy for Resistance . . . . . . . . . . . . . . . . . 57
4.3 Parasitic Resistance Network ......................... 58
4.4 Parameter Impacts on INV-Rsd ........................ 61
4.4.1 Fin height................................ 62
4.4.2 Poly height ............................... 63
4.4.3 High poly height ............................ 63
4.4.4 Low poly height ............................ 65
4.4.5 MD height ............................... 65
4.4.6 Poly to MD Spacing .......................... 66
4.4.7 Key Parameters............................. 66
4.5 Parameter Impacts on INV-Rmd ........................ 68
4.5.1 Fin height................................ 68
4.5.2 Poly height ............................... 68
4.5.3 High Poly height ............................ 71
4.5.4 Low Poly height ............................ 71
4.5.5 MD height ............................... 73
4.5.6 MD to PO Spacing........................... 73
4.5.7 Key Parameters............................. 74
4.6 Parameter Impacts on INV-Rg......................... 74
4.6.1 Fin height................................ 75
4.6.2 Poly height............................... 75
4.6.3 High poly height ............................ 78
4.6.4 Low poly height ............................ 78
4.6.5 MD height ............................... 80
4.6.6 MD to Poly Spacing .......................... 80
4.6.7 Key parameters............................. 82
4.7 Resistance Sensitivities with More Realistic Material Properties . . . . . . 82
4.7.1 Resistance Sensitivities for INV, ND2 and NR2 . . . . . . . . . . . 84
4.8 Summary .................................... 86
5 Parasitic Impacts on Gate Performance 87
5.1 Introduction................................... 87
5.2 Impacts on INV Performance ......................... 88
5.3 ND2 and NR2 Gates .............................. 92
5.3.1 Automated SPICE Subcircuit Generation and Verifications . . . . . 97
5.4 Transistor Size Impacts on Delay ....................... 98
6 Conclusions and Future Work ....................... 100
6.1 Conclusions ...................................100
6.2 Future Work ..................................101
References ..................................102

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