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[5] Synopsys. (2008), HSPICE User Guide: Simulation and Analysis, Synopsys, 2008 [6] Ashis Kumar Mal, Anindya Sundar Dhar, “Modified Elmore Delay Model for VLSI Interconnect,” Circuits and Systems (MWSCAS), 2010. [7] Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru, “Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no.11, Nov 1998. [8] Kenichi Miyaguchi , “Modeling FinFET Metal Gate Stack Resistance for 14nm Node and Beyond,” IC Design & Technology (ICICDT), International Conference on, 2015 [9] G.-L. Chen, “Exploring FinFET Cell Layout to Minimize Parasitic Impacts,” master thesis, NTHU, July 2016 [10] H.-Y. Lin, “Parasitic Impacts on Sub-20nm FinFET Transistors,” master thesis, NTHU, July 2016
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