近年來，電晶體微縮的進展被一些挑戰所阻礙，例如：漏電流、短通道效應，以及製造上的困難。鰭式場效電晶體 (FinFET) 是一個對於在平面式電晶體的製程微縮中所遇到的短通道效應而言具有可行性的解決方案，而且已被廣泛地採用在先進的互補式金屬氧化物半導體 (CMOS) 製程中。
然而，FinFET的獨特物理結構與佈局也帶來了新的缺陷模式，以至於可能造成在傳統March測試演算法下難以檢測的錯誤。在先進製程中，輕微的缺陷越來越常發生，有更高的可能性導致動態錯誤 (dynamic faults)，在某些業界案例中也顯示可能是測試遺漏 (test escape) 的根本原因。記憶體的動態錯誤需要多個操作 (multiple-operation) 的序列 (sequence) 來偵測，而多個操作的序列擁有更高的測試演算法複雜度，也就意味更多的測試時間與測試成本，因此較不易被實作。於是，我們需要一個更有效的測試方法來檢測記憶體電路中的難測缺陷。
在這篇論文中，我們探討在一個基於FinFET的靜態隨機存取記憶體 (SRAM) 單元 (cell) 中可能的缺陷與其位置，在電路模擬中分析其錯誤行為，找出會導致動態錯誤的缺陷做為測試標的，以及提出一個能在無需增加測試時間下增強錯誤涵蓋率 (fault coverage) 的內建自我測試 (BIST) 方案。我們提出的內建自我測試電路是以偵測位元線 (bit line) 在放電階段的延遲來檢測輕微缺陷。我們提出的方法能夠在一個讀取操作下檢測出所有標的缺陷，這可以減少所需的測試演算法複雜度以及測試時間。再者，我們所提出的內建自我測試電路，其實體佈局只有非常小的4%面積成本。並且，內建自我測試電路的整合對記憶體電路的性能影響也非常低。我們所提出的內建自我測試方案可以結合傳統的測試演算法一併使用，例如March C-，在不增加測試演算法複雜度之下增強錯誤涵蓋率，以降低缺陷水平 (defect level)。

Recently, the progress of transistor scaling is obstructed by some challenges, e.g., leakage power, short-channel effects, and fabrication difficulties. FinFET is a feasible solution to short-channel effects that has been encountered by planar transistors during process scaling, and is widely adopted in advanced CMOS technologies.
However, the special physical structure and layout of FinFET also bring new defect models that may cause hard-to-detect faults by conventional March algorithms. In advanced manufacturing processes, weak defects occur more and more frequently, which are more probable to cause dynamic faults and can be the root cause of test escapes as shown by some industrial studies. Memory dynamic faults require multiple-operation sequences to sensitize, which are hard to implement due to higher test complexity and hence higher test time and cost. Therefore, a more effective test methodology is required for covering those hard-to-detect defects in memory circuits.
In this work, we investigate possible defects and injection site candidates in a FinFET 6T-SRAM cell, analyze their fault behaviors, find out target defects that will cause dynamic faults, and propose a Built-In Self-Test (BIST) scheme to enhance fault coverage without increasing test time. The proposed BIST circuit detects weak defects by capturing the delay behavior in the bit line discharging phase. The proposed approach is able to detect all target defects with only one read cycle, which reduces the required test algorithm complexity and hence reduces test time. In addition, the physical implementation of the proposed BIST circuit shows a small area overhead of 4%. Furthermore, the performance impact of BIST insertion is very low as well. This BIST scheme can be used with classical March algorithms, such as the March C-, to extend fault coverage beyond static single cell or coupling faults, thus reduce the defect level without increasing test complexities.

摘要 i
Abstract ii
List of Figures v
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Objective 3
1.3 Organization 3
Chapter 2 Defect & Functional Fault Models for FinFET Device 4
2.1 FinFET Device 4
2.2 FinFET Defect Modeling 5
2.3 Defect Injection in a FinFET-Based SRAM Cell 7
2.4 Functional Fault Models 10
Chapter 3 Fault Simulation 14
3.1 Simulation Setup 14
3.1.1 Circuit Under Test (CUT) 14
3.1.2 Test Algorithm 17
3.1.3 SPICE Simulation Setup 18
3.2 Fault Simulation Result 19
3.2.1 Fault Simulation Result of Fin Resistive-Open Defects 19
3.2.2 Fault Simulation Result of Fin Stuck-On Defects 33
3.3 Summary of Fault Simulation 53
Chapter 4 Proposed BIST Scheme 55
4.1 Previous Works 55
4.2 SRAM Defects, Dynamic Faults & The Bit-Line Discharge Delay 58
4.3 The Proposed BIST Circuit 60
4.4 BIST Integration & Timing Control in SRAM 63
Chapter 5 Experimental Result 69
5.1 Experimental Setup 69
5.2 Experimental Result 71
5.3 Physical Implementation 81
5.3.1 Layout & Area Overhead 81
5.3.2 Performance Impact 83
Chapter 6 Conclusion and Future Work 84
6.1 Conclusion 84
6.2 Future Work 85
References 86

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