在系統晶片(SoC)中，各式的模組單元皆擁有著不同的頻寬(bandwidth)需求。晶片網路(NoC) 具有著可高度擴充性(scalability)及可提供高頻寬的特性(high bandwidth)，因此在系統晶片中，成為了替代傳統匯流排的選擇。

Rocket Chip 平臺是一個以Chisel(下一代新的暫存器層級的硬體描述語言)所寫成的開源系統晶片產生器。而目前Rocket Chip平臺只提供了傳統匯流排來來作為IP間的資訊傳遞與溝通，隨著平台中IP數目的增加，使用者就可能遇到頻寬及擴充性等問題。因此，在此論文中，我們實做出了晶片網路，並將它整合到了Rocket Chip 平臺中。我們採用了OpenSoC Fabric計畫中的晶片網路架構，為了將此晶片網路架構與Rocket Chip 平臺做整合，我們因此對它做了些修正。 除了修正工作外，它缺少了一個很重要的元件，因此，我們另外設計出了網路介面模組(NI)。網路介面模組主要負責將Rocket Chip中所使用的TileLink匯流排協定訊息轉譯成能夠於晶片網路中傳遞的封包型式，同時也扮演了硬體加速器與晶片網路間的溝通介面。 透過此溝通介面，可將原本使用TileLink匯流排協定的各式IP與晶片網路作串聯，使得IP間可成功地透過晶片網路作資訊傳遞與溝通。

我們另外設計出了數個IP，包含了bridge DMA、 線性整流函數(ReLU)加速器、 最大池化(Max Pooling)加速器，以整合到基於晶片網路所實作出的平臺，並用來確認正確性與效能。最後，透過一些實驗，我們將展示出加速器分別透過TileLink介面的匯流排與晶片網路作為資訊傳遞的效能差異。

Network-on-chip (NoC) has emerged as an alternative to traditional bus interconnect for its scalability and high bandwidth, especially in a SoC with a large number of modules with different bandwidth requirements.

In this thesis, we implemented a NoC fabric on Rocket Chip platform, an open-source system-on-chip generator in Chisel (a next-generation RTL language). Based on OpenSoC Fabric project, we designed a network interface (NI) to translate Rocket Chip TileLink bus protocol into packets for NoC transport, and also a packet interface for hardware accelerator modules.

To validate our NoC-based platform, several IPs including bridge DMA, ReLU, and Max Pooling engines are designed to integrate together with a NoC. In the experiments, we will show and compare the performance of the accelerators with TileLink bus and SoC Fabric NoC.

1 Introduction 10
1.1 Thesis Organization 11
2 Background 12
2.1 Chisel 12
2.2 Rocket Chip 13
2.3 TileLink 14
2.3.1 TileLink Protocol Conformance Levels 14
2.3.2 TileLink Uncached Lightweight 15
2.4 OpenSoC Fabric 16
2.5 Convolutional Neural Networks(CNN) 18
2.5.1 Rectified Linear Unit (ReLU) 18
2.5.2 Max Pooling 18
3 Proposed Platforms with Distinct Interconnect - NoC And Bus 20
3.1 Accelerators Communication with Bus on RISC-V Rocket Chip Platform Overview 20
3.2 Bridge DMA 23
3.2.1 Operation Size Discussion 24
3.2.2 Efficiently Utilize Burst Property 25
3.3 Global Buffer And Fragmentor 26
3.3.1 Global Buffer 26
3.3.2 Fragmentor 27
3.4 Accelerator 29
3.4.1 Benifit of Possessing Master Port And Slave Simultaneously 30
3.5 Data Bus 31
3.6 Accelerators Communication with NoC on RISC-V Rocket Chip Platform Overview 31
4 NoC Implementation on Rocket Chip Platform 34
4.1 Approach for Connectiong NoC(OpenSoC Fabric) to Rocket Chip Platform 34
4.2 Router And Mesh NoC 36
4.2.1 Router Architecture 36
4.2.2 Mesh NoC Construction And Router Revision 37
4.3 Injection Queue And Ejection Queue 39
4.3.1 Injection Queue 39
4.3.2 Ejection Queue 40
4.4 Flit Format 41
4.5 Network Interface (NI) 43
4.5.1 Master Network Interface(MNI) 43
4.5.2 Slave Network Interface(SNI) 45
4.6 Request Packet And Response Packet 49
5 Accelerator Implementation 51
5.1 ReLU Engine 51
5.1.1 ReLU Calculation Core 53
5.2 Max Pooling Engine 54
5.2.1 Implementation Idea for Max Pooling Calculation 56
5.2.2 Max Pooling Calculation Architecture 64
5.3 Blocking Feature 67
6 Experiment Result And Verification 68
6.1 Latency Analysis 68
6.1.1 Max Pooling Calculation Latency Measurement 68
6.1.2 ReLU Latency Measurement 68
6.1.3 DMA Operation Latency Measurement 70
6.2 Single Frame Experiment 70
6.2.1 Experimental Environment 70
6.2.2 Experiment Result 71
6.2.2.1 Max Pooling Parameter versu Execution time 72
6.2.2.2 Accelerator Version Comparison for Window Size = 2 ; Stride =
1 and Window Size = 3 ; Stride = 1 73
6.3 Multi-core versus Multi-frame Experiment 74
6.3.1 Experimental Environment 74
6.3.2 Total Execution Time Result 78
6.4 DMA Function Verification 78
7 Conclusions and Future Work 79
7.1 Conclusions 79
7.2 Future Work 79

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