本篇論文提出詳細的管線式類比數位轉換器設計流程，分別從頻域與時域的觀點來設計與考量電路運作與其效能，並且採用電路模擬軟體完成整體電路設計與晶片佈局。本次設計取樣頻率為40MHz的10位元管線式類比數位轉換器，採用TSMC 0.18µm 1P6M製程，其供應電壓為1.8V。類比數位轉換器採用1.5-bit/stage技術，克服比較器偏移產生的誤差，並且可以減輕比較器所需要的規格。開關式電容電路採用疊接式米勒補償來提高運算放大器的穩定度。
此類比數位轉換器運用電路模擬軟體設計。經由佈局後模擬結果可得知，當操作電壓為1.8V，取樣頻率為40MHz，輸入頻率為奈奎斯特取樣率，其訊號對雜訊失真比為60.804dB，總功率消耗為67.5mW，FOM的效能為1.88pJ/conversion-step，晶片核心面積為1.66mm2。

This thesis presents the design flow of Pipeline ADC that discusses the operation and effect of circuit in aspects of time and frequency domains in detail by applying circuit simulation tools to finish the design and the layout of whole ADC. The 10-bit 40MHz pipelined analog-to-digital converter was fabricated in a TSMC 0.18µm 1P6M process with 1.8V supply voltage. Design concept of 1.5-bit/stage is employed to mitigate the error effects of comparator offset. Moreover, the 1.5-bit/stage is configured to decrease the speciation of comparators. In the circuit level, the cascade miller compensation is adopted for the design of the switch-capacitor circuit to enhance the stability of operational amplifier. At a 1.8-V supply and 40MS/s, the simulation result achieves an SNDR of 60.804 dB while consumes 67.5 mW, resulting in a figure of merit (FOM) of 1.88 pJ/conversion-step. The ADC core occupies an active area of 1.66 mm2.

中文摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究動機 1
1.2 論文結構 3
第二章 電路架構概論 4
2.1 類比數位轉換器參數介紹 4
2.1.1 取樣頻率(Sampling Rate)和輸入頻率(Input Rate) 4
2.1.2 解析度(Resolution) 4
2.1.3 輸入範圍(Input Range) 4
2.1.4 最低有效位元(Least Signification Bit) 5
2.1.5 增益誤差(Gain Error) 5
2.1.6 偏移誤差(Offset Error) 5
2.1.7 微分非線性誤差(Differential Nonlinearity) 6
2.1.1 積分非線性誤差(Integral Nonlinearity) 7
2.1.2 遺失碼(Missing Code) 8
2.1.3 訊號對雜訊比(Signal-to-Noise Ratio) 8
2.1.4 總諧波失真(Total Harmonic Distortion) 10
2.1.5 訊號對雜訊失真比(Signal-to-Noise and Distortion Ratio) 10
2.1.6 有效位元數(Effective Number of Bit) 11
2.1.7 無雜訊動態範圍(Spurios Free Dynamic Range) 11
2.1.8 動態範圍(Dynamic Range) 11
2.2 類比數位轉換器架構介紹 12
2.2.1 理想類比數位轉換器 12
2.2.2 快閃式類比數位轉換器(Flash ADC) 13
2.2.3 連續漸進式類比數位轉換器(SAR ADC) 14
2.2.4 管線式類比數位轉換器(Pipeline ADC) 15
第三章 管線式類比數位轉換器之分析 18
3.1 簡介 18
3.2 1.5-bit/stage演算法 18
3.3 運算放大器所需要規格 24
3.3.1 運算放大器的頻寬 24
3.3.2 運算放大器的增益 25
3.3.3 運算放大器的迴轉率 25
3.3.4 運算放大器規格計算 26
3.4 運算放大器種類 29
3.4.1 單級運算放大器 29
3.4.2 雙級運算放大器 31
3.4.3 共模回授電路 33
3.5 模擬結果 34
第四章 管線式類比數位轉換器之設計 37
4.1 簡介 37
4.2 雜訊 37
4.3 取樣保持電路 39
4.3.1 內部開關 39
4.3.2 開關式電容電路 48
4.4 子類比數位轉換器 52
4.4.1 比較器電路 52
4.4.2 1.5-bit 子類比數位轉換器 55
4.4.3 2-bit快閃式類比數位轉換器 56
4.5 MDAC 58
4.6 時脈產生器 61
4.7 數位電路 63
4.7.1 暫存器 63
4.7.2 加法器 64
4.8 模擬結果 66
4.8.1 動態分析 67
4.8.2 靜態分析 67
4.9 電路佈局圖 68
第五章 量測環境與結果 71
5.1 量測設定 71
5.2 量測結果 74
5.2.1 靜態參數量測 74
5.2.2 動態參數量測 74
5.2.3 結果分析 75
第六章 結論 80
參考文獻 81

[1] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design,” John Wiley & Sons, Inc., 1997.
[2] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, ”CMOS Data Converter For Communication,” Kluwer Academic Publishers, Boston, 2002.
[3] Behzad Razavi, ”Design of Analog CMOS Integrated Circuit,” McGraw-Hill, Boston,2001.
[4] John P. Uyemura, ”CMOS Logic Circuit Design,” Kluwer Academic Publishers, Boston, 1999.
[5] R. Jacob Baker, “CMOS: Circuit Design, Layout, and Simulation,” Wiley-IEEE Press, 2005.
[6] Andrew Masami Abo,”Design for Reliability of Low-voltage, Switched-capacitor Circuits,” Ph.D. Thesis, University of California, Berkeley, 1999.
[7] Fayomi, C.J.B.; Roberts, G.W.; Sawan, M., ”Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization,” ISCAS Circuits and Systems, Vol. 3 , pp. 2200-2203, May 2005.
[8] Byung-Moo Min, P. Kim, D. Boisvert, and A. Aude, “A 69 mW 10 b 80 MS/s pipelined CMOS ADC,” IEEE International Solid-State Circuits Conference, 2003
[9] T. B. Choand P. R. Gray, “A 10b, 20MSample/s, 35mW Pipeline A/D Converter,” IEEE Journal of Solid-State Circuits, vol.SC-30, no.5, pp.166- 172, Mar. 1995.
[10] S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, T.R. Viswanathan,“A 10-b 20Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits,Vol. 27, pp.351-358, March 1992.
[11] Yong-In Park, S .Karthikeyan, F. Tsay, and E. Bartolome, “A 10-b 100- MSample/s CMOS pipelined ADC with 1.8 V power supply,” IEEE International Solid-State Circuits Conference, Feb. 2001
[12] J. Steensgaard, ”Bootstrapped low-voltage analog switches,” in Proc. IEEE int. Symp.Circuits and System (ISCAS), vol.2, pp. 29-32, May 1999.
[13] Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,”IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318–325, Mar. 2000.
[14] P. C. Yu, and H. S. Lee, “2.5-V, 12-b, 5MS/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996.
[15] G. Hoogzaad, R. Roovers, “A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1796 – 1802, Dec. 1999.
[16] T. Cho and P. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 30, no.3, pp. 166–172, Mar. 1995.
[17] J. Doernberg, H-S. Lee, D. A. Hodges, “Full-Speed Testing of A/D Converters,” IEEE J. Solid-State Circuits, vol. SC-19, no. 6, Dec. 1984.
[18] C. Ojas, L. R. Carley, “Analysis of Switched-Capacitor Common-Mode Feedback Circuit,” IEEE Transactions on Circuit and Systems, Vol. 50, pp.3226-334, Dec. 2003.
[19] P. R. Surkanti, A. Garimella, and P. M. Furth, “Pole-zero analysis of multi-stage amplifiers: A tutorial overview,” in IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, Aug. 2011, pp. 1–4.
[20] P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer, “Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers,” IEEE Trans. Circuits Syst. I, vol. 51, no. 2, pp. 275–285, Feb. 2004.
[21] I. Ahmed, and D. A. Johns, “A high bandwidth power scalable sub-sampling10-bit pipelined ADC with embedded sample and hold,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1638-1647, July 2008.
[22] J. Shen and P. Kinget, “A 0.5-V 8-bit 10-Ms/s pipelined ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 787–795, Apr. 2008.
[23] K. Chandrashekar, M. Corsi, J. Fattaruso, and B. Bakkaloglu, “A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 8, pp. 602–606, Aug. 2010.
[24] D. Gubbins, B. Lee, P. Hanumolu, and U. Moon, “Continuous-time input pipeline ADCs,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1456– 1468, Aug. 2010.