本論文提出一個使用四十奈米製程，操作於兩百百萬頻率的十二位元類比數位轉換器，以雙通道的時序交錯混合式每週期雙位元連續漸進逼近與數位斜坡技巧實現。
傳統循序漸進逼近式類比數位轉換器會因比較時間與電容穩定時間等原因使其操作速度較慢，本論文採用時序交錯架構與雙位元產出手法來加快操作速度，而時序交錯架構中的雙通道架構完全相同，並輪流交替進行收斂行為；雙位元產出則使用一雙通道共用的參考電壓數位類比轉換器與額外兩個離散時間比較器來達成。
而為了解決一般循續漸近式類比數位轉換器在高解析度規格下，電容切換所需能耗與離散時間比較器能耗的問題，本架構採用直接切換手法與兩階段式操作。直接切換手法能減少切換之電容，降低其切換能耗。而兩段式架構操作中第一階段使用在低解析度規格下擁有較佳能源效率的循續漸近式類比數位轉換器並搭配雙位元產出，經過冗餘位元位移後進行第二階段收斂，第二階段採用交互骨牌數位斜坡手法以連續時間比較器代替離散時間比較器降低能源消耗，並採用時域內差手法增加額外的一位元以壓低量化雜訊，達到較好的有效位元數。
藉由以上手法，使本架構能在較少的能耗下達到兩百百萬頻率的中間偏高速操作頻率，並能達到11位元以上的有效位元，並可應用在高速通訊系統中。

This thesis presents a hybrid ADC constructed with two-channel time-interleaved structure, with each channel composed by subrange SAR-based two-bit-per-cycle coarse and alternate-domino digital-slope fine, contribute resolution at 12-bit and operation frequency at 200MHz by TSMC 40nm process.
Conventional SAR ADC has a limit operation frequency due to the comparison time and DAC settling time. To solve this problem, the proposed ADC is composed by time-interleaved structure with two-bit-per-cycle method. The both channel are identically, it works alternatively with the sample clock in 50% duty cycle. The two-bit-per-cycle uses an extra two channel co-use reference DAC and two extra discrete-time comparator to contribute the function.
The another problem of conventional SAR is that the switching energy increases exponentially with the resolution, also, the discrete-time comparator costs dramatic energy to suppress the noise at the high resolution. To solve these problem, the direct-switching and subrange structure is used. The direct-switching can switch lease capacitance to reduce the switching energy. The subrange structure is constructed by SAR-based two-bit-per-cycle coarse and alternate-domino digital slope fine with the redundancy between coarse and fine. The SAR-base two-bit-per-cycle has well power efficiency in low resolution, and the continuous-time comparator of the digital slope has better power efficiency than the discrete-time comparator in high resolution with short operation time. Furthermore, a time-domain interpolation bit is insert into the fine ADC to suppress the quantization noise, make the ENOB better.
The method and structure mentioned below contribute the 11-bit ENOB 200MHz operation frequency ADC with low power, which can applicate in high speed communication system.

ABSTRACT II
致謝 IV
CONTENTS VI
LIST OF FIGURES X
LIST OF TABLES XIII
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.3 PERFORMANCE METRICS OF ADC 3
1.3.1 Nyquist Criterion 3
1.3.2 Nyquist Criterion 4
1.3.3 Quantization error 4
1.3.4 Offset and Gain Error 6
1.3.5 Differential Nonlinearity 7
1.3.6 Integral Nonlinearity 8
1.3.7 Signal-to-Noise Ratio 9
1.3.8 Effective Number of Bit (ENOB) 9
1.3.9 Figure of Merit 9
1.4 TARGET SPECIFICATION 10
1.5 THESIS ORGANIZATION 11
CHAPTER 2 SUCCESSIVE APPROXIMATION REGISTER ADC OVERVIEW 12
2.1 INTRODUCTION 12
2.2 OPERATION PROCEDURE OF CONVENTIONAL SAR ADC 13
2.3 CONSIDERATIONS OF SAMPLE AND HOLD 14
2.3.1 Turn-on Resistance 14
2.3.2 Charge Injection 15
2.3.3 Clock Feedthrough 15
2.3.4 KT/C Noise 16
2.4 CONSIDERATIONS OF CAPACITIVE DAC 17
2.4.1 DAC Parasitic Capacitance 18
2.4.2 DAC Capacitor Mismatch 18
2.4.3 Settling Time 18
2.5 CONSIDERATIONS OF COMPARATOR 19
2.5.1 Input Offset 20
2.5.2 Kickback Noise 20
2.6 SAR CONTROL LOGIC 21
2.7 SUMMARY 22
CHAPTER 3 CIRCUIT DESIGN CONSIDERATIONS 24
3.1 THE BOTTLENECKS OF SAR ADC 24
3.1.1 Operation Speed 24
3.1.2 Power Consumption in High Resolution 24
3.2 SOLUTION OF THE BOTTLENECKS 25
3.2.1 Solution to Enhance Operation Speed 25
3.2.2 Solution to suppress switching power consumption 26
3.2.3 Solution to suppress the comparator power consumption 26
3.3 PROPOSED TWO-BIT-PER-CYCLE COARSE ADC 27
3.3.1 Mechanism of Proposed Two-bit-per-cycle Method 27
3.3.2 Direct Switching Method 29
3.3.3 Non-ideal Effect and Residue Range 30
3.4 PROPOSED ALTERNATE-DOMINO DIGITAL SLOPE 31
3.4.1 Digital Slope 31
3.4.2 Alternate-domino Switching 32
3.4.3 Time Domain Interpolation 33
3.5 REDUNDANCY AND CALIBRATION 33
3.6 PROPOSED ADC 35
3.7 SUMMARY 36
CHAPTER 4 CIRCUIT IMPLEMENTATION 37
4.1 ARCHITECTURE OF PROPOSED ADC 37
4.2 DESIGN OF SAMPLE AND HOLD 38
4.3 DESIGN OF CAPACITIVE DAC 39
4.4 DESIGN OF DISCRETE-TIME COMPARATOR 40
4.4.1 Calibration 41
4.5 DESIGN OF DIRECT SWITCHING LOGIC 41
4.6 DESIGN OF CONTINUOUS-TIME COMPARATOR 42
4.6.1 Calibration 43
4.7 DESIGN OF ALTERNATE-DOMINO SWITCHING LOGIC 44
4.8 DESIGN OF REDUNDANT SHIFT LOGIC 45
4.9 DESIGN OF ENCODER 46
4.10 SUMMARY 47
CHAPTER 5 SIMULATION RESULTS 48
5.1 PRE-LAYOUT SIMULATION 48
5.2 POST-LAYOUT SIMULATION 50
5.3 NON-IDEAL EFFECTS 52
5.3.1 Increase of Power Consumption 52
5.3.2 Switching Timing Offset 52
5.3.3 D Flip-flop Latching Offset 53
5.4 MATLAB MODEL SIMULATION 54
5.5 PERFORMANCE SUMMARY AND COMPARISON 55
5.6 SUMMARY 56
CHAPTER 6 CONCLUSION AND FUTURE WORK 57
6.1 CONCLUSION 57
6.2 FUTURE WORK 57
BIBLIOGRAPHY 58

[1] B. Murmann, "ADC Performance Survey 1997-2016," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
[2] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd ed.: WILEY, 2010.
[3] MICROCHIP, DC Specifications http://microchipdeveloper.com/adc:adc-dc-spec
[4] R. H. Walden, "Analog-to-digital converter survey and analysis," in IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, Apr 1999.
[5] D. J. Deng, K. C. Chen and R. S. Cheng, "IEEE 802.11ax: Next generation wireless local area networks," 10th International Conference on Heterogeneous Networking for Quality, Reliability, Security and Robustness, Rhodes, 2014, pp. 77-82.
[6] B. Verbruggen, K. Deguchi, B. Malki and J. Craninckx, "A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2.
[7] Yuan Zhou, Benwei Xu and Yun Chiu, "A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2.
[8] J. P. Mathew, L. Kong and B. Razavi, "A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C66-C67.
[9] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed.: McGraw-Hill 2002.
[10] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta, "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2008, pp. 244-610.
[11] P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators," IEEE Trans. Circuits and Systems II, Express Briefs, vol. 53, pp. 541-545, Jul. 2006.
[12] C. C. Liu, S. J. Chang, G. Y. Huang and Y. Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[13] C. C. Liu, M. C. Huang and Y. H. Tu, "A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016.
[14] P. Harpe, E. Cantatore and A. van Roermund, "A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3011-3018, Dec. 2013.
[15] T. Miki et al., "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015.
[16] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York, NY, USA: Wiley, 1997, ch. 13, sec. 1, pp. 487–489.
[17] P. J. A. Harpe, C. Zhou, K. Philips, and H. de Groot, “A 0.8-mW 5-bit 250-MS/s time-interleaved asynchronous digital slope ADC,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2450–2457, Nov. 2011.
[18] G.-Y. Huang, C.-C. Liu, Y.-Z. Lin, and S.-J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," in IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2009, pp. 157-160.