在現今的系統晶片、微處理器、通訊積體電路晶片以及其它時間相關的之電路設計中，延遲鎖定迴路(delay-locked loops, DLLs)及相位鎖定迴路(phase-locked loops, PLLs)已被大量且廣泛的使用於消除時間偏差。而在供應電壓越來越低的先進製程中，全數位延遲鎖定迴路(all-digital-delay-locked-loop, ADDLL) 亦有日漸取代傳統類比延遲鎖定迴路的趨勢。隨著技術不斷的發展，超寬範圍的延遲鎖定迴路也越顯重要。
在本篇論文當中，我們提出了一個全新的延遲線架構，特色是可以支援超廣延遲範圍以及快速鎖定的功能。
透過電晶體層級的模擬，我們驗證此架構可以在台積電九十奈米製程下支援10 MHz到1 GHz的單頻時脈操作。同時，與前做相較最多可以減少百分之八十八的鎖定時間。

In today's system-on-a-chip (SOC), microprocessors, communication ICs, and other time-related circuit designs, Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs) are widely used to eliminate the clock skew. In advanced COMS processes where supply voltages are getting lower and lower, all-digital-delay-locked-loop (ADDLL) has been increasingly replacing traditional analog DLLs. As technology continues to evolve, an ultra-wide range of DLLs will also become a trend in the future.
In this paper, we present a new delay line architecture that features an ultra-wide delay range and fast locking functionality.
With transistor-level simulation, we show that our architecture supports single-frequency clock operating from 10 MHz to 1 GHz using TSMC 90 nm process. Compared to the previous works, the lock time can be reduced by up to 88 %.

Abstract........................................................i
摘要...........................................................ii
致謝..........................................................iii
Content........................................................iv
List of Figures................................................vi
List of Tables................................................vii
Introduction....................................................1
I.1 Motivation and Background...........................1
I.2 Thesis Organization.................................3
Chapter II
Preliminaries...................................................4
II.1 Delay locked loop..................................4
II.2 A highly resilient DLL using ping-pong delay line..6
Chapter III Architecture and Operation of Delay Line........7
III.1 Base idea – linear search.........................8
III.1.1 Architecture of long-range tuning block.........8
III.1.2 Operation of long-range tuning block...........10
III.2 Time multiplexed prediction......................12
III.2.1 Architecture of time multiplexed prediction....12
III.2.2 Operation of TMP...............................13
III.3 Hybrid Long Range Tuning Block...................16
III.3.1 Architecture of hybrid long-range tuning block.16
III.3.2 Operation of Hybrid Long-range Tuning Block....19
Chapter IV
Experimental Results...................................20
IV.1 Table of hybrid long range tuning block...........20
IV.2 Layout of hybrid long range tuning block..........21
Chapter V
Conclusion.............................................22
References.....................................................23

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