三維積體電路是個能夠使得電晶體的密度跟隨著摩爾定律，在每十八個月變為之前的兩倍的做法，而整合型扇出型晶圓級晶片封裝(InFO WLCSP)是其中一種最有前途的封裝方式。在整合型扇出型晶圓級晶片封裝裡面會存在著許多晶片間的連線。我們無法直接探測這些連線，進而導致1-2%的測試覆蓋率損失。因此，晶片需要有些自我測試(BIST)或其他測試(DfT)電路去測試這些連線。對於斷路以及大量漏電的錯誤，傳統的測試方法已經能夠有效的解決。於是，我們這次所要針對的是小量漏電的錯誤。在本篇碩士論文當中，我們提出了一種方法去量測晶片間連線的小量漏電，這個方法使用了邊緣掃描的測試介面。由於邊緣掃描是個許多人採用的標準，所以這個方法能夠很容易的被整合至其他電子產品中。除了四個必要的端點之外，我們增加了一個參考電流輸入。使用者可以輸入電流並與漏電進行比較。對於輸入端的邊緣掃描單元(BSC)來說，相較於傳統的邊緣掃描單元，我們新增了兩個或的邏輯閘、一個選擇器、以及一個由交通大學的洪浩喬教授與他的學生林龍逸所設計的電流量化器。我們實作了一個測試晶片來驗證我們的設計，使用的是1P9M 90奈米的CMOS製程。量測結果顯示我們提出的方法是能夠量測晶片間連線的漏電。在量測結果中可以看到，電流量化器的解析度能達到六位元，並擁有128奈米安培的動態範圍。

3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore’s law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2% test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In the thesis, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer, which is designed by Prof. Hao-Chiao Hong and his student Long-Yi Lin, are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-poly-nine-metal (1P9M) 90nm CMOS technology. Test results show that the proposed scheme is able to measure the leakage current of the interconnect. In our measurement result, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.

摘要 2
Abstract ii
Contents iii
List of Figures v
List of Tables viii
Chapter 1 Introduction 1
1.1 3D-IC, InFO WLCSP, and Interconnect Test 1
1.2 Objective 4
1.3 Organization 5
Chapter 2 Test Schemes for Inter-Die Interconnects in 2.5D and 3D Packages 6
2.1 Boundary Scan Overview [12, 16] 6
2.2 Proposed Test Scheme 10
Chapter 3 Proposed Architecture and Circuit 14
3.1 Architecture 14
3.2 Input and Output EBSC 16
3.3 Electrical Model of Interconnect [14] 17
3.4 Current Digitizer [14] 18
Chapter 4 Test Flow and Simulation Results 20
4.1 Multi-Interconnect and Single-Interconnect Measurement 20
4.2 Calibration for Current Digitizer 23
4.3 Procedure of Leakage Measurement 25
4.4 Simulation Results 32
Chapter 5 Measurement Result 39
5.1 Chip Implementation 39
5.2 Measurement Environment Setup 43
5.3 Measurement Result 46
Chapter 6 Conclusion and Future Work 53
6.1 Conclusion 53
6.2 Future Work 53
Bibliography 55

[1] R. Courtland, "Transistors could stop shrinking in 2021," IEEE Spectrum, vol. 53, no. 9, pp. 9-11, Sept. 2016.
[2] E. J. Marinissen and Y. Zorian, "Testing 3D chips containing through-silicon vias," in Proc. International Test Conference (ITC, Nov. 2009), pp. 29-38.
[3] H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, "Wafer Level Chip Scale Package copper pillar probing," in Proc. International Test Conference (ITC), Oct. 2014, pp. 1-6.
[4] M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, "Novel adaptive probing for wafer level chip scale package," in Proc. Joint e-Manufacturing and Design Collaboration Symposium (eMDC) & International Symposium on Semiconductor Manufacturing (ISSM), Sept. 2015, pp. 1-5.
[5] K. S.-M. Li, C. Su, Y.-W. Chang, C.-L. Lee and J. E. Chen, "IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2513-2525, Nov. 2006.
[6] P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, "On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification," in Proc. Asian Test Symposium (ATS), Nov. 2009, pp. 450-455.
[7] P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, "On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding," in Proc. VLSI Test Symposium (VTS), April. 2010, pp. 263-268.
[8] M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, "Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 11, pp. 1718-1727, Nov. 2011.
[9] L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, and W.-T. Cheng, "Oscillation-Based Prebond TSV Test," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 9, pp. 1440-1444, Sept. 2013.
[10] S.-Y. Huang and L.-R. Huang, "PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning," IEEE Design & Test, vol. 31, no. 4, pp. 36-42, Aug. 2014.
[11] S. Deutsch and K. Chakrabarty, "Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators," in Proc. IEEE International Test Conference (ITC), Oct. 2015, pp. 1-10.
[12] IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE, New York, July 2001.
[13] C. Wang, J. Zhou, R. Weerasekera, B. Zhao, X. Liu, P. Royannez, and M. Je, "BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 139-148, Jan. 2015.
[14] L.-Y. Lin, H.-C. Hong, and C.-W. Wu, “Circuit Design of A Test Scheme for Pre-Bond Test of TSVs in 3-D IC”, VLSI Test Technology Workshop (VTTW), July. 2016.
[15] C. Maunder, "The Joint Test Action Group," Computer-Aided Engineering Journal, vol. 3, no. 4, pp. 121-122, Aug. 1986.
[16] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Elsevier (Morgan Kaufmann), San Francisco, 2006.