在過去的三十年中，半導體產業大量將電晶體的小型化。根據摩爾定律，電晶體尺寸的縮小使得在晶片上可放置超過數億個電晶體。積體電路（IC）的多樣化且增加的功能和降低的成本讓半導體產業和用戶帶來了許多優勢。電晶體的微縮帶來了一些好處，例如:製造成本低，數據速度快，器件尺寸小並且能夠同時執行多個任務。隨著電晶體縮小到10nm技術節點，以矽為基礎的元件已經達到了基本的物理極限。創新的三維結構，如double、triple、 fin-type、nanosheet和nanowire（FET）也引起了眾多公司極大的興趣。新穎結構，例如 tunnel FET和Junctionless FET被開發出來。在通道材料方面，高遷移率通道材料（如Ge和III-V材料，如InGaAs）被認為是最有希望能取代Si材料，因為它們的遷移率大於Si的遷移率。
因此，本文研究了未來電晶體技術的可能性。我們將研究分為五個部分。第一部分，我們研究了錐形矽FinFET的鰭片形狀對5-nm節點CMOS技術中元件性能的影響。模擬結果表明，增加鰭片高度可以有效地提高飽和電流。然而，更高的鰭高度意味著更大的高寬比，因此在製造過程中不容易製造。另一方面，通過加寬底部鰭寬度也可以改善飽和電流。然而，它可能不是一個好的選擇，因為為外延源和漏極提供了更大的橫截面元件區域。調整頂部鰭寬可能是獲得當前增益的最佳選擇。此外，閾值電壓沒有顯著影響，並且有利於源極 - 漏極外延。通過仔細控制鰭片高度和頂部鰭片寬度，可以非常好地預測元件性能。基於以上結果，摩爾定律甚至可以工作10nm節點CMOS技術。
第二部分，我們研究了三種器件模式下的新型納米片（NS) FET器件結構：使用3D TCAD於次5nm技術節點的反轉模式（IM），累積模式（AC）和無結模式（JL）模擬。使用12nm的柵極長度（LG），EOT 0.8 nm和三個垂直堆疊的通道來模擬器件。仿真結果表明，IM，AC和JL NSFET的有效驅動電流（IEFF）相互之間相似。然而，小信號AC分析表明JL NSFET的總閘極電容小於IM和AC器件。 JL NSFET的柵極中的串連空乏區電容和氧化物電容可以減小總閘極電容。 JL NSFET的載流子集中在NS溝道層的中心並形成部分空乏。降低電容可以有效地將CMOS反向器的時間延遲提高4％左右。這些特性表明，JL NSFET可以交替使用，以提高器件性能，同時為預期的高性能邏輯器件應用提供更小的電容。
第三部分，我們提出使用Ge-cap量子井（QW）FinFET進行5nm CMOS電路模擬，這是一個Si通道，在鰭片通道的三個側面包裹著Ge。模擬結果表明，Ge-cap FinFET結構表現出比純Si，純Ge和Si-cap FinFET結構更好的性能。通過優化Si鰭片寬度和Ge-cap厚度，nFET和pFET的導通電流可不透過改變總鰭片寬度（FWp = FWn）也可以是對稱的。由於在Ge和Si異質結構的最低導帶中形成QW，Ge-cap nFinFET中的電子集中在Si溝道中，而Ge-cap pFinFET中的電洞由於在Ge價中形成的QW而優選留在Ge表面中。帶。該器件的物理研究使得設計規則與CMOS反向器和SRAM應用技術的應用相關。
第四部分，我們利用三維TCAD模擬研究了Si基板上垂直堆疊InGaAs / InAlAs / InP雙量子阱（DQW）FinFET的性能。 In0.53Ga0.47As和In0.52Al0.48As分別用作量子阱和阻擋材料。兩種材料都與Si基板上的InP緩衝層材料晶格匹配。該器件的閘極長度（LG）為15nm，閘極堆疊（Al2O3 / HfO2）為1nm / 2nm（EOT~0.75 nm）。模擬結果表明，與單量子阱（SQW）器件相比，採用雙通道量子阱（超晶格結構）可以提高飽和電流。 DWQ的電子密度傾向於在InGaAs層中定位為量子阱通道，因此允許更好地控制電子行為。元件特性表明，Si基板上的DQW FinFET可以交替使用，以增強元件性能，適用於未來的高性能和低功耗邏輯器件應用。
最後一部分，我們研究了非常陡的次臨界擺幅斜率元件，隧道FET（TFET）。 TFET中的載波通過帶間隧穿（BTBT）機制從源極到汲極傳輸。為了實現TFET的高飽和電流，它關鍵取決於傳輸概率TWKB。我們採用非局域BTBT模型，通過包括量子效應模擬，應用於閘極長度為10nm的三維Ge-Si異質結TFET，與Si TFET相比。結果表明，由於較低的帶隙和較大的隧道窗口，Ge-Si TFET優於Si TFET。在導通狀態下，Ge-Si TFET的BTBT產生率高於Si TFET。最高的BTBT生成速率位於源極和通道交界點，其峰值靠近柵極電介質。

Over the last three decades, the semiconductor industry has availed massively from the 　transistor miniaturization. The shrinking of transistor dimensions enables more than hundreds of million transistors to be placed on a single chip as Moore's law observed. The increased functionality and reduced cost of the enormous diversification of integrated circuits (IC) have brought its own advantages to the semiconductor industry and end users. Some of the major benefits gained as a result of transistor scaling are a low cost of fabrications, increased data speed, small device dimension, and the capability to carry out multiple tasks simultaneously. As the transistor scaling down to 10 nm technology node, the silicon-based FET had reached the fundamental physics and process technology limits. Innovative three-dimensional structures such as double-, triple-, fin-type, nano-sheet, and nanowire field-effect transistors (FET) have been also of great interests. Novel nanodevices structure, such as tunnel FET, Junctionless FET have been also developed. On the channel materials perspective, high mobility channel materials such as germanium and III-V materials, like InGaAs are believed to be the most promising candidates because their bulk mobility is larger than that of silicon.
Therefore, we study the possibility of future transistor technology in this dissertation. We divided our study into five parts. The first part, we investigated the effect of fin shape of tapered Silicon FinFETs on the device performance in 5-nm node CMOS technology. The simulation results show that increasing the fin-height can enhance the saturation current effectively. However, a higher fin-height means that a larger aspect ratio, thus it is not easy to fabricate in the manufacturing process. On the other hand, the saturation current also can be improved by widening the bottom fin-width. Nevertheless, it may not be a good choice because lets a larger cross-section device area for epitaxy source and drain. Tuning the top fin-width may be the best choice to have a current gain. Moreover, the threshold voltage has no significant impact and it is good for source-drain epitaxy. By careful control of the fin-height and top fin-width, the device performance can be predicted very well. As the results, Moore's law still can work even 5-nm node CMOS technology.
The second part, we study novel Nanosheet (NS) FET device structure in three device modes: Inversion Mode (IM), Accumulation Mode (AC), and Junctionless Mode (JL) for the potential sub-5-nm technology node using 3D TCAD simulation. The devices are simulated with gate lengths (LG) of 12 nm, EOT 0.8 nm, and three vertically stacked channels. The simulation result shows that the effective drive current (IEFF) of IM, AC, and JL NSFET are relatively similar to each other. However, the small signal AC analysis shows that the total gate capacitance of JL NSFET is smaller than IM and AC devices. The series of depletion and oxide capacitance in the gate of JL NSFET can reduce the total gate capacitance. The carriers of JL NSFET concentrate in the center of NS channel layers and forms partial depletion. Reducing the capacitance can effectively improve the intrinsic time delay of CMOS inverter around 4%. These characteristics indicate that the JL NSFET can be alternated to enhance the device performance with less capacitance for prospective high-performance logic device applications.
The third part, we propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (FWp = FWn). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant to the application of the CMOS inverter and SRAM application technology.
The fourth part, we study the performance of vertically stacked InGaAs/InAlAs/InP Double Quantum Well (DQW) FinFETs on Si substrate using 3D TCAD simulation. In0.53Ga0.47As and In0.52Al0.48As were used as the quantum well and the barrier material, respectively. Both materials are lattice matched to the InP buffer layer material on the Si substrate. The device is simulated with gate lengths (LG) of 15 nm and gate stack (Al2O3/HfO2) of 1nm/2nm (EOT~ 0.75nm). The simulation results reveal that by using double channel quantum well (superlattice structure) can enhance the saturation current compared to Single Quantum Well (SQW) device. The electron density of DWQ prefers to localize in the InGaAs layer as the quantum well channel, thus allows greater control over the electron behavior. The device characteristics indicate that the DQW FinFET on Si substrate can be alternated to enhance the device performance for future high-performance and low-power logic device applications.
The last part, we investigated very steep inverse subthreshold swing slope devices, Tunnel FET (TFET). The carriers in TFET transport from source to channel by the band-to-band tunneling (BTBT) mechanisms. To realize high saturation currents of TFET, it critically depends on the transmission probability, TWKB. We employed the nonlocal BTBT model applied to three-dimensional Ge-Si heterojunction TFET with gate length 10 nm compared with Si TFET by including quantum effects simulation. The results show that the Ge-Si TFET outperforms Si TFET because of the lower band gap and larger tunneling windows. BTBT generation rates of Ge-Si TFET are higher than Si TFET in the on-state condition. The highest BTBT generation rates are located in the source and channel junction and its peaks close to the gate dielectric.

中文摘要 iv
Abstract viii
Acknowledgement xii
Contents xiii
List of Tables xv
List of Figures xvi
Chapter 1 Introduction 1
1-1 Logic Device Scaling Challenges and Opportunities 1
1-2 Device Structures in Advanced Nano-Transistor 6
1-2-1 Multi-Gate (MuG) FET 9
1-2-2 Tunnel FET (TFET) 11
1-2-3 Junctionless (JL) FET 14
1-3 High Mobility Channel Material 19
1-3-1 Germanium 19
1-3-2 III-V materials 20
1-4 TCAD Simulation 22
1-5 Motivation 22
1-6 Thesis Objectives and Organization 22
Chapter 2 Tapered Si FinFET 25
2-1 Literature Review 25
2-2 Simulation Approach 27
2-2-1 Device Structure 27
2-2-2 Simulation Model 29
2-3 Results and Discussion 30
2-3-1 Effect of Variation Fin-Height (FH) 31
2-3-2 Effect of Variation Top Fin-Width (FWT) 32
2-3-3 Physical Properties Analysis of Different FWT and FH 34
2-3-4 Device Parameter Variation of Different FWT and FH 38
2-4. Summary 40
Chapter 3 Stacked Nanosheet FET 41
3-1 Literature Review 41
3-2 Device Structure and Simulation Model 43
3-3 Results and Discussion 46
3-3-1 Static Performances 46
3-3-2 Dynamic Performances 52
3-4 Conclusion 58
Chapter 4 Ge-cap Quantum Well FinFET 59
4-1 Literature Review 59
4-2 Device structure and simulation models 62
4-3 Results and discussion 64
4-4 Summary 75
Chapter 5 InGaAs FinFET on Si Substrate 76
5-1 Literature Review 76
5-2 Device Structure and Simulation Approach 78
5-3 Results and Discussion 81
5-4 Summary 87
Chapter 6 Ge-Si Heterojunction Nanowire Tunnel FET 88
6-1 Literature Review 88
6-2 Band-to-Band Tunneling (BTBT) Theory 89
6-3 Simulation Methods 92
6-4 Results and Discussions 94
6-5 Summary 102
Chapter 7 Conclusions and Future Works 103
7-1 Conclusions 103
7-2 Future Works 103
References 104
簡歷 123
著作目錄 (Publication list) 126

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