在這篇論文中提出一個創新架構之低電壓輸出電容切換式帶差參考電路，此架構能夠提供低於雙極性接面型電晶體之基極-射極電壓的輸出及較低的溫度係數（Temperature coefficient）。
本篇架構使用運算放大器（OPA）、雙極性接面型電晶體（BJT）及切換式電容。運算放大器能夠避免雜散電容及供應電源鏈波對於輸出電壓的影響，同時利用電容的切換，使輸入偏差電壓抵銷（input offset voltage cancellation）。切換式電容能夠使輸出電壓值能夠降低至雙極性接面型電晶體之基極-射極電壓（VBE）以下。
在內文中會介紹此電路的實現方法及考量，最後附上本論文使用TSMC0.18μm 1P6M技術設計和晶片量測結果。本電路適用於1.5V~1.8V之供應電源，在-30℃~70℃的溫度範圍內之溫度係數（Temperature coefficient）為117.8 ppm/℃。在1kHz的正弦波擾動的情況下，電源電壓抑制比（Power supply rejection ratio）為-77.7dB。多組晶片量測得到的標準差為1.35mV，亦可表示為0.319%。

In this thesis, a novel architecture of low voltage output switched capacitor bandgap reference is proposed.This study can provide low temperature coefficient and low voltage output which can be lower than VBE. This study uses operational amplifier, BJT and switched capacitor. Operational amplifier can prevents the influence to output voltage from parasitic capacitor and power supply ripple. And it can also cancel input offset voltage by the switching of capacitor. This paper can provide the consideration of the circuit. In the end of this paper, TSMC 0.18μm 1P6M technology is discussed with design flow and measurement results. The measurement result shows that this circuit can be used from 1.6V~1.8V supply voltage. The temperature coefficient is 117.8 ppm/℃ from -30℃~70℃, and the PSRR is -77.7dB with 1kHz sin wave noise. The standard deviation is 1.35mV or 0.319% by the measurement from several chips.

致謝 i
中文摘要 ii
Abstract ⅲ
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 研究方法 2
1.3 論文架構 3
第二章 帶差參考電路簡介 4
2.1 帶差參考電路的驅動原理 4
2.2 帶差參考電路的特性參數 7
第三章 電路設計與實現 9
3.1 低電壓輸出電容切換式帶差參考電路架構簡介 9
3.2 低電壓輸出電容切換式帶差參考電路介紹 12
3.2.1 低電壓輸出電容切換式帶差參考電路整體架構分析 12
3.2.2 與溫度無關之電流源架構 18
3.2.3 運算放大器 20
3.2.4 偏壓電路 22
3.2.5 數位控制電路 23
3.3 電路模擬結果 25
3.3.1 運算放大器 25
3.3.2 低電壓輸出電容切換式帶差參考電路 26
3.3.3 使用與溫度無關電流源之低電壓輸出電容切換式帶差參考電路 31
第四章 量測環境與結果 37
4.1 量測環境規劃 37
4.1.1 量測環境 37
4.1.2 量測規劃與架設 39
4.2 低電壓輸出電容切換式帶差參考電路量測結果 41
4.2.1 溫度係數 41
4.2.2 電源電壓抑制比 43
4.2.3 製程變異量的分佈及標準差 46
4.2.4 供應電壓依賴 48
4.2.5 量測結果與文獻比較 49
第五章 結論與未來展望 51
5.1 結論 51
5.2 未來展望 52
參考文獻 53

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