本篇論文針對低密度奇偶檢查碼 (Low-density parity-check codes, LDPC codes)階層式架構(Layered scheduling)解碼器分別提出幾種改良演算法、硬體架構以及電路設計的方法來提升的解碼吞吐量以及降低硬體複雜度。由於LDPC 解碼演算法之解碼複雜度與大量儲存資訊的要求主要都是來自檢查節點更新的計算，因此本文第一個方法提出了只存第二小值(second-minimum-only, SMO)的正規化最小和演算法(normalized Min-Sum, NMS)來降低檢查節點更新的儲存量且不會有太大的解碼效能衰退。

為了能夠達到更高解碼吞吐量的解碼器且不影響解碼效能，一種時間維度(Time-domain, TD)的訊號處理方式與電路設計敘述在本篇論文的第四章中。透過TD訊號處理技巧使得LDPC解碼器在檢查節點(check node, CN)運算的時間可以大幅下降。一個Q-based的階層解碼器架構被用來減少C2V資訊儲存量。本篇論文利用IEEE 802.15.3c標準做為展示TD-based 的技術，此顆晶片採用CMOS 90奈米製程，核心電路面積為2.25 mm$^2$。量測結果在1.05V的操作電壓下，操作頻率最高可以達157 MHz，此時的解碼吞吐量為5.28 Gbps，能量消耗與能源效率分別為182 mW、34.47 pJ/b。這是第一顆利用TD訊號處理方式可以實作在通訊標準的晶片設計。

相較於二進制(binary)運算，利用高維度的有限域(high-order finite field)運算的非二進制(non-binary, NB)LDPC碼可以擁有更好的解碼效能，然而其運算複雜度與儲存資訊需求亦提高不少。本篇論文第五章節針對Trellis Min-Max (TMM)演算法提出一個適合硬體設計的低複雜度演算法以及高硬體效率的解碼器架構來達到傳統NB-LDPC解碼器難以做到的高吞吐量與低硬體面積的需求。為了減少CN資訊的儲存量以及避免解碼效能衰退，論文提出了適合硬體設計的CN資訊的壓縮與解壓縮的技術，此方法亦可減低運算需求。此外，一個有效率的後驗概率({\it a posteriori} log-likelihood ratio)計算方式也被提出來達到減低運算複雜度。為了做到更高的解碼吞吐量，我們提出第一個實作在NB-LDPC解碼器且不會影響解碼效能的提早終止方式。利用與CN運算共用計算模組，此提早終止方式不需要花費太多額外的硬體代價以及不需增加額外運算時間。以上技術利用90奈米製程展示在32-ary (837, 726)的NB-LDPC碼，其解碼器硬體面積為6.86 mm$^2$，模擬的操作頻率最高可達526.32 MHz，在提早終止尚未啟動時，解碼吞吐量為1.64 Gbps，如果在$E_b/N_0 = $ 4.5 dB情況下啟動提早終止功能時，解碼吞吐量可以再提升至4.68 Gbps。與過去文獻比較，即使不使用提早終止功能，本解碼器仍可達到最高解碼吞吐量以及最高的硬體效能。

In order to further enhance the hardware efficiency for a low-density parity-check (LDPC) decoder, the decoding algorithm, together with the associated architecture should be modified.
No matter whether the LDPC deocder is binary or non-binary(NB), the process for updating the check-node (CN) unit dominates the decoding complexity and memory requirements.
For a binary LDPC decoder, a second minimum-only Normalized Min-Sum (NMS) algorithm is proposed such that the first minimum values are not stored without introducing any notable degradation in error-rate performance.
Therefore, only second minimum values, together with the associated index of the first minimum value need to be stored.



In order to achieve a further high-throughput LDPC decoder while preventing any degradation in error-rate performance, a time-domain (TD) signal processing scheme is proposed.
The latency for determining the first two minimum values required in the CN unit is significantly reduced through TD processing.
A layered Q-based decoding architecture, together with the associated scheduling, is proposed in order to reduce the amount of memory used for check-to-variable (C2V) storage.
As a proof of concept, a TD-based multi-mode LDPC decoder applicalbe for high-speed IEEE 802.15.3c-compliant devices is designed and fabricated in a 90-nm CMOS process.
The LDPC decoder integrates 495K logic gates in an area of 2.25 mm$^2$, and achieves a throughput of 5.28 Gbps at 157 MHz from a 1.05 V supply voltage.
The power and normalized energy dissipation are 182 mW and 34.47 pJ/b, respectively.
The proposed LDPC decoder is more hardware and energy efficient than its previous digital counterparts, and is able to support long codes for practical applications, which is still unfeasible for the current state-of-the-art TD-based LDPC decoders.

A modified Trellis Min-Max (T-MM) algorithm, together with the associated architecture for NB-LDPC codes, is able to provide a reduction in the memory requirements for CN messages through an efficient indirect method, while enhancing the error-rate performance using appropriate decompression.
A method of updating the {\it a posteriori} log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity.
In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions from the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error-rate performance.
As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process.
The proposed decoder achieves a throughput of 1.64 Gbps at 526.32 MHz with 8 iterations, and has an area of 6.86 mm$^2$.
When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gbps.
The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the current state-of-the-art decoders even when the ET scheme is not enabled.

1 Introduction 1
2 Review of Low density parity check (LDPC) coding 6
2.1 QC-LDPC codes . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 NMS-based layered decoding . . . . . . . . . . . . . . . . . . . . 7
2.3 Check-node unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Low-complexity Normalized Min-Sum (NMS) Algorithm 11
3.1 Low-complexity NMS algorithm . . . . . . . . . . . . . . . . . . 11
3.1.1 Different upper limits for the first two minimum values . 12
3.1.2 Dynamic normalization factor and CNU architecture . . 15
3.2 Second-minimum-only (SMO) NMS algorithm . . . . . . . . . . 17
3.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 High-throughput Time-domain (TD) LDPC Decoder Design 26
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 TD-based Check-node unit . . . . . . . . . . . . . . . . . . . . . 29
4.2.1 Conventional TD-based MVF . . . . . . . . . . . . . . . 29
4.2.2 Proposed TD-based MVIG . . . . . . . . . . . . . . . . . 30
4.2.3 Area- and time-efficient MVIG . . . . . . . . . . . . . . . 35
4.2.4 Hardware-efficient CNU . . . . . . . . . . . . . . . . . . 39
4.3 TD-based multimode LDPC decoder . . . . . . . . . . . . . . . 42
4.3.1 A Q-based layered decoder architecture . . . . . . . . . . 42
4.3.2 Multi-mode decoder architecture . . . . . . . . . . . . . 49
4.3.3 Chip implementation . . . . . . . . . . . . . . . . . . . . 52
4.4 Chip Verication . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 A hardware-effieiency Trellis Min-Max Algorithm for Non-
Binary LDPC Decoder 63
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2 Non-binary LDPC decoding . . . . . . . . . . . . . . . . . . . . 67
5.2.1 Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.2 CN updating for T-MM algorithm [43] . . . . . . . . . . 69
5.3 Hardware-friendly T-MM algorithm . . . . . . . . . . . . . . . . 75
5.3.1 CN message reduction . . . . . . . . . . . . . . . . . . . 75
5.3.2 C2V message recovery . . . . . . . . . . . . . . . . . . . 83
5.3.3 LLR updating in the delta domain . . . . . . . . . . . . 89
5.3.4 Early Termination Scheme . . . . . . . . . . . . . . . . . 92
5.4 Efficient Layered Decoder architecture . . . . . . . . . . . . . . 94
5.4.1 Efficient layered decoder architecture . . . . . . . . . . . 94
5.4.2 CN unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4.3 TD-based CN unit . . . . . . . . . . . . . . . . . . . . . 104
5.4.4 Delta-domain based LLR updating and VN units . . . . 107
5.5 Performance evaluation . . . . . . . . . . . . . . . . . . . . . . . 111
6 Conclusion 121

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