相變化記憶體(phase change memory, PCM)是一種具潛力的新興記憶體，其具潛力的因素包括微縮性、獨立寫入、非揮發性以及高寫入效率。雖然目前具潛力的結果被論證於單階儲存(single-level cell, SLC)，未來在多階儲存(multi-level cell, MLC)的履行將會減少每位元成本，亦是勢在必行的。在此博士論文裡探討多階儲存相變化記憶體的效能來尋找潛在議題及提出解決方案。具體分為以下三項重要的議題，電阻飄移(resistance drift) 、多階儲存寫入(MLC programming)與多次使用造成記憶體細胞老化變異。
在多階儲存相變化記憶體中，電阻飄移的現象來自結構鬆弛(structural relaxation)造成嚴重地減少感測幅度。因此，原始錯誤率(raw-bit-error rate)在常溫兩小時後可達〖10〗^(-2)，亦在典型修正碼(error correcting code, ECC)修正容忍範圍外。在此，我們提出電阻飄移補償(resistance drift compensation, RDC)機制，以中度寫入脈波做部分地溶解單胞非晶體〖Ge〗_2 〖Sb〗_2 〖Te〗_5(GST)區域，利用GST非晶體與晶體的熱傳導差異來達成。此RDC機制已被論證在室溫和85°C下有效減少超過100倍原始錯誤率(RBER)。此外，我們針對三個實際考量做延伸討論，包括RDC對單胞壽命影響、多階儲存單胞分佈演化以及錯誤形式。我們也證實RDC機制可降低錯誤率至〖10〗^6個週期。
目前許多寫入機制已經被提出和運算的基準做比較，其中包括能量、延遲、能量和延遲乘積(energy delay product, EDP)。然而，這些基準無法反映由電阻飄移在多階儲存變相化記憶體中造成的實際資料維護(data integrity maintenance, DIM)成本。在此我們提出一種寫入-維護(program-maintenance, PM)基準重新評估反复寫入機制(iterative programming scheme)在使用不同脈波形式情況下之效益。結果顯示，寫入-維護基準在使用最優化的脈波形式下，相對於傳統設置(Set)與重設(Reset)脈波形式優於86.7%。此外，在其他兩項合作專案裡，我們探討使用變量的讀取電壓和多次使用導致細胞老化異變的資訊來增加存取容量。
雖然變化相單胞記憶體寫入次數已被論證可達〖10〗^9個週期，但排列的寫入次數由於多次使用導致細胞老化異變而明顯減少。我們探討單胞老化異變的影響對於單胞的特性和多階單胞的可靠性。針對前者，我們提出循環警示點(cycle alarm point)來監控單胞老化異變，並透過原處熱退火(in-situ-self-anneal)論證恢復老化的可行性。對於後者，我們提出老化修正(stress-trim)，目的為執行部分排列的變相化單胞記憶體特性校正。我們論證此種方法有效減少多階儲存寫入電流振幅範圍40%並延緩錯誤時間(time to failure)150倍。
變相化記憶體被列選為具潛力的記憶體，然而仍然還有許多挑戰等待發現。這些挑戰包括電阻飄移現象、多階儲存寫入效益與多次使用導致細胞老化變異現象。在此博士論文中提出細節的特性分析和實際的技術幫助多階儲存相變化記憶體更邁進商品化。

Phase change memory (PCM) is a promising emerging memory candidate for several reasons, including scalability, bit-alterability, non-volatility, and high program speed. While promising results were demonstrated in single-level cell (SLC) mode, the implementation of multi-level cell (MLC) topology to reduce the cost-per-bit will be inevitable in the future. This PhD dissertation emphasized on investigating the multilevel cell (MLC) PCM performances to identify potential issues and propose practical solutions. Specifically, three critical issues were identified and studied, including resistance drift, MLC programming, and stress-induced cell variations.
In MLC PCM, the resistance drift phenomenon caused by structural relaxation dramatically diminishes the sensing margin. As a result, the raw-bit-error-rate (RBER) reaches 10-2 after two hours of retention time. This is beyond the correction ability of typical error-correcting-codes (ECC). In our work, we proposed a resistance drift compensation (RDC) scheme to utilize an intermediate programming pulse to partially melt the amorphous GST region of the cell. This is accomplished by exploiting the thermal conductivity difference between amorphous and crystalline GST material. It was demonstrated that the RDC scheme is capable of reducing the RBER by over 100 times under both room temperature and 85˚C. In addition, we expand the investigations with three practical considerations, including the impact of RDC on cell endurance, MLC distribution evolution, and error pattern. We also demonstrated the RDC scheme to be effective up to 106 cycles.
Several programming schemes had been proposed and compared using evaluation metrics that involves energy, delay, or energy-delay product (EDP). These metrics, however, does not reflect the data integrity maintenance (DIM) overhead caused by the resistance drift phenomenon in MLC PCM. In our work, we evaluated the PM metric of iterative programming scheme with various pulse shapes. Our results showed that the PM metric of the optimized pulse shape is better than those of the conventional SET and RESET pulse shapes up to 86.7%. Furthermore, in two other collaborative works, we investigated the possibility of using variable read voltage and cycling-stress information to extend storage capacity.
PCM cell endurance had been demonstrated up to 109 cycles, array endurance is significantly shorter due to cycling-induced variations. We investigated the impact of cycling-induced variations on cell characteristic and MLC reliability. In the former, we proposed a cycle alarm point (CAP) inspection to monitor the cycling degradation and demonstrated the feasibility of recovering cycling-induced degradation through in-situ-self-anneal (ISSA) procedure. In the latter, we proposed a Stress-trim procedure that purposely enforce a certain amount of cycling stress on the PCM array to align the PCM cells’ device characteristics. We demonstrated this approach can reduce MLC program amplitude range by 40% and extends MLC time to failure by nearly 150X.
PCM is a promising emerging memory candidate, however there are several challenges that still must be addressed. These challenges include resistance drift phenomenon, MLC programming, and stress-induced cell variations. This dissertation provides detailed characterization and practical techniques that helps bringing MLC PCM one step toward commercialization.

Table of Content
Abstract 1
Acknowledgement 3
List of Figures 8
List of Figures 17
Chapter 1 Introduction to Phase Change Memory 18
1.1 Background 18
1.2 History and Recent Development 3
Chapter 2 Multilevel Cell Phase Change Memory 9
2.1 SLC and MLC PCM 9
2.2 MLC PCM Desirable Characteristics 12
2.3 Resistance Drift 14
2.4 Cycling-induced Variation 17
Chapter 3 Resistance Drift Compensation Scheme 22
3.1 Challenges of Conventional Approaches 22
3.2 Resistance Drift Compensation Scheme 25
3.2.1 MLC PCM Chip and Evaluation Platform 26
3.2.2 Resistance Drift Compensation Mechanism 29
3.3 Measurement Results 33
3.3.1 Resistance Drift Compensation Characteristic 33
3.3.2 Time and Cell-State Independencies 37
3.3.3 Impact on Cell Resistance and Endurance 39
3.4 Additional Considerations 41
3.4.1 Multiple RDC Iteration Consideration 42
3.4.2 Cycling-Induced Degradation Consideration 44
3.4.3 Longer Retention Time Consideration 46
3.5 Simulation Results on Latency and Power Overheads 47
3.6 Chip Demonstration and Summary 51
Chapter 4 Multi-level Cell Phase Change Memory Program and Read Schemes 54
4.1 Dual-mode Phase Change Memory using a Novel Background Storage Scheme 55
4.1.1 Confined Bottom-Electrode Cell Structure 55
4.1.2 Novel Stressing Mode Storage 56
4.1.3 The Proposed Background Data Write and Read 58
4.1.4 Measurement Results 59
4.2 Greater than 2-bits-per-cell Phase Change Memory using a Novel Multi-Independent-Window Sensing Scheme 64
4.2.1 Sidewall Bottom Electrode Cell Structure 64
4.2.2 Multi-Independent-Window Sensing Scheme 66
4.2.3 Drift Tolerance Evaluation 71
4.3 A Retention-Aware Multilevel Cell Phase Change Memory Program Evaluation Metric 73
4.3.1 Multilevel Cell Phase Change Memory Program Schemes and Measurement Results 73
4.3.2 Multilevel Cell Phase Change Memory Evaluation Metric 79
Chapter 5 Phase Change Memory Cycling-Induced Degradation 82
5.1 Inspection and Annealing Procedure to Recover Phase Change Memory from Cycling-Induced Degradations 83
5.1.1 Detailed R-I Curve Analysis 83
5.1.2 Cycle Alarm Point Inspection 87
5.1.3 In-Situ Self-Anneal Method 88
5.2 A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multilevel Cell Performance 93
5.2.1 Phase Change Memory Variation 94
5.2.2 The Stress-Trim Procedure 94
5.2.3 Measurement Results 96
Chapter 6 Conclusion and Future Work 103
6.1 Conclusion 103
6.2 Future Works 105
List of Publications 108
List of Granted Patents 110
Reference 111

[1] R. F. Freitas and W. W. Wilcke, “Storage-class memory: The next storage system technology,” IBM Journal of Research and Development, vol. 52, no. 4-5, pp. 439-447, July 2008.
[2] W. S. Khwa, J. Y. Wu, T. H. Su, H. P. Li, M. BrightSky, T. Y. Wang, T. H. Hsu, P. Y. Du, S. Kim, W. C. Chien, H. Y. Cheng, R. Cheeks, E. K. Lai, Y. Zhu, M. H. Lee, M. F. Chang, H. L. Lung, and C. Lam, "A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications," in IEEE International Electron Devices Meeting, San Francisco, CA, 2014, pp. 29.8.1-29.8.4.
[3] W. S. Khwa, J. Y. Wu, T. H. Su, M. H. Lee, H. P. Li, Y. Y. Chen, M. BrightSky, T. Y. Wang, T. H. Hsu, P. Y. Du, W. C. Chien, S. Kim, H. Y. Cheng, E. K. Lai, Y. Zhu, M. F. Chang, H. L. Lung, and C. Lam, "A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances," in IEEE International Memory Workshop, Monterey, CA, 2015, pp. 1-4.
[4] Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Cheng, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, and Chung Lam, "7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100x for storage-class memory applications," in IEEE International Solid-State Circuits Conference, San Francisco, CA, 2016, pp. 134-135.
[5] Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Cheng, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, and Chung Lam, "A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100 times for Storage Class Memory Applications," IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 218-228, Jan. 2017.
[6] W. S. Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lan Lung, and Chung Lam, "A Retention-Aware Multilevel Cell Phase Change Memory Program Evaluation Metric," IEEE Electron Device Letters, vol. 37, no. 11, pp. 1422-1425, Nov. 2016.
[7] J. Y. Wu, M. H. Lee, W. S. Khwa, H. C. Lu, H. P. Li, Y. Y. Chen, M. BrightSky, T. S. Chen, T. Y. Wang, R. Cheek, H. Y. Cheng, E. K. Lai, Y. Zhu, H. L. Lung, and C. Lam, "A double-density dual-mode phase change memory using a novel background storage scheme," in IEEE Symposium on VLSI Technology and Circuits, Honolulu, HI, 2014, pp. 1-2.
[8] J. Y. Wu, W. S. Khwa, M. H. Lee, H. P. Li, S. C. Lai, T. H. Su, M. L. Wei, T. Y. Wang, M. BrightSky, T. S. Chen, W. C. Chien, S. Kim, R. Cheek, H. Y. Cheng, E. K. Lai, Y. Zhu, H. L. Lung, and C. Lam, "Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme," in IEEE Symposium on VLSI Technology and Circuits, Kyoto, 2015, pp. 94-95.
[9] H. S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase Change Memory," Proceedings of the IEEE, vol. 98, no. 12, pp. 2201-2227, Dec. 2010.
[10] D. Ielmini, “Threshold switching mechanism by high-field energy gain in the hopping transport of chalcogenide glasses,” Physics Review B, vol. 8, pg. 035308, July 2008.
[11] A. T. Waterman, “Positive ionization of certain hot salts, together with some observations on the electrical properties of molybdenite at high temperatures,” Philosophical Magazine and Journal of Science, pg. 225-247, March 1917.
[12] A. T. Waterman, “The electrical conductivity of molydenite,” Physics Review Letters, vol. 21, pg. 540-549, May 1923.
[13] Stanford R. Ovshinsky, “Reversible electrical switching phenomena in disordered structures,” Physics Review Letters, vol. 21, No. 20, pg. 1450-1453, November 1968.
[14] R. G. Neale, D. L. Nelson, and G. E. Moore, “Nonvolatile and reprogrammable, the read mostly memory is here”, Electronics, vol. 43, no. 20, pg. 56-60, Sept. 1970.
[15] P. Clarke (December 2, 2010). Phase Change memory found in handset [Online]. Retrieved from http://www.eetimes.com/document.asp?doc_id=1258042.
[16] Samsung Announces Production Start-up of its Next-generation Nonvolatile Memory PRAM (2009, September 22) [Online]. Received from www.samsung.com/semiconductor/insights/news/4097.
[17] Micron Announces Agreement to Acquire Numonyx (February 9, 2010) [Online]. Received from http://investors.micron.com/releasedetail.cfm?releaseid=443974
[18] Numonyx Introduces New Phase Change Memory Devices (April 21, 2010) [Online]. Received from http://investors.micron.com/releasedetail.cfm?releaseid=466859.
[19] Micron Announces Availability of Phase Change Memory for Mobile Devices (July 18, 2012) [Online]. Received http://investors.micron.com/releasedetail.cfm?releaseid=692563.
[20] Chris Mellor (January 14, 2014). Micron: Hot DRAM. We don’t need no steenkin’ PCM [Online]. Received http://www.theregister.co.uk/2014/01/14/phase_change_micron_drops_phase_change_memory_products/.
[21] Intel and Micron Produce Breakthrough Memory Technology (July 28, 2015) [Online]. Received https://newsroom.intel.com/news-releases/intel-and-micron-produce-breakthrough-memory-technology/
[22] P. Clarke (July 31, 2015). Patent Search Supports View 3D XPoint Based on Phase-Change Memory [Online]. Received http://www.eetimes.com/author.asp?section_id=36&doc_id=1327313
[23] Les Tokar, Intel Optane Memory Review – 1.4GB/S Speed & 300K IOPS for $44 (April 24, 2017) [Online]. Received http://www.thessdreview.com/our-reviews/ngff-m-2/intel-optane-memory-module-review-32gb-every-pc-user-know/
[24] Kang-Deog Suh, Hyung-Hoon Suh, Young-Ho Lim, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, Suk-Chon Kwon, Byung-Soon Choi, Jin-Sun Yum, Jung-Hyuk Choi, Jang-Rae Kim, and Hyung-Kyu Lim, “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme,” IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
[25] N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, E. Eleftheriou, “Programming algorithms for multilevel phase-change memory,” in IEEE International Symposium of Circuits and Systems, Rio de Janeiro, 2011, pp. 329-332.
[26] M. Boniardi, D. Ielmini, S. Lavizzari, A. L. Lacaita, A. Redaelli, and A. Pirovano, “Statistics of resistance drift due to structural relaxation in phase-change memory arrays,” IEEE Transaction on Electron Devices, vol. 57, no. 10, pp. 2690–2696, Oct. 2010.
[27] A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti, and R. Bez, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Transaction on Electron Devices, vol. 51, no. 5, pp. 714–719, May 2004.
[28] D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, “Physical mechanism and temperature acceleration of relaxation effects in phase change memory cells,” in IEEE International Reliability Physics Symposium, Phoenix, AZ, 2008, pp. 597–603.
[29] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Temperature acceleration of structural relaxation in amorphous Ge2Sb2Te5,” Applied Physics Letter, vol. 94, no. 19, pg. 193511, April 2008.
[30] W. K. Njoroge, H.-W. Wöltgens, and M. Wuttig, “Density changes upon crystallization of Ge2Sb2.04Te4.74 films,” Journal of Vacuum Science and Technology A, vol. 20, no. 1, pg. 230, Jan. 2002.
[31] I. V. Karpov, M. Mitra, D. Kau, G. Spadini, Y. A. Kryukov, and V. G. Karpov, “Fundamental drift of parameters in chalcogenide phase change memory,” Journal of Applied Physics, vol. 102, no. 12, pg. 124503, Dec. 2007.
[32] J. Im, E. Cho, D. Kim, H. Horii, J. Ihm, and S. Han, “A microscopic model for resistance drift in amorphous Ge2Sb2Te5,” Current Applied Physics, vol. 11, no. 2, pp. 82–84, Feb. 2011.
[33] D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, "Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part I: Experimental Study," IEEE Transactions on Electron Devices, vol. 56, no. 5, pp. 1070-1077, May 2009.
[34] H. Pozidis, N. Papandreou, A. Sebastian, T. Mittelholzer, M. BrightSky, C. Lam, and E. Eleftheriou, "A Framework for Reliability Assessment in Multilevel Phase-Change Memory," in IEEE International Memory Workshop, Milan, May 2012, pp. 1-4.
[35] Jing Li et al., "Explore physical origins of resistance drift in phase change memory and its implication for drift-insensitive materials," in International Electron Devices Meeting, Washington, DC, 2011, pp. 12.5.1-12.5.4.
[36] Y. N. Hwang et al., "MLC PRAM with SLC write-speed and robust read scheme," in IEEE Symposium on VLSI Technology, Honolulu, 2010, pp. 201-202.
[37] W. Xu and T. Zhang, "A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift," IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 8, pp. 1357-1367, Aug. 2011.
[38] M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian and V. Srinivasan, "Efficient scrub mechanisms for error-prone emerging memories," in IEEE International Symposium on High-Performance Comp Architecture, New Orleans, Feb. 2012, pp. 1-12.
[39] H. Y. Cheng, T. H. Hsu, S. Raoux, J. Y. Wu, P. Y. Du, M. Breitwisch, Y. Zhu, E. K. Lai, E. Joseph, S. Mittal, R. Cheek, A. Schrott, S. C. Lai, H. L. Lung, and C. Lam, “A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material,” in IEEE International Electron Device Meeting, Washington, DC, 2011, pp. 3.4.1-3.4.4.
[40] S. C. Lai, S. Kim, M. BrightSky, Y. Zhu, E. Joseph, R. Bruce, H. Y. Cheng, A. Ray, S. Raoux, J. Y. Wu, T. Y. Wang, N. Sosa Cortes, C. M. Lin, Y. Y. Lin, R. Cheek, E. K. Lai, M. H. Lee, H. L. Lung, and C. Lam, "A scalable volume-confined phase change memory using physical vapor deposition," in IEEE Symposium on VLSI Technology, Kyoto, 2013, pp. 132-133.
[41] P. Y. Du, J. Y. Wu, T. H. Hsu, M. H. Lee, T. Y. Wang, H. Y. Cheng, E. K. Lai, S. C. Lai, H. L. Lung, S. Kim, M. BrightSky, Y. Zhu, S. Mittal, R. Cheek, S. Raoux, E. Joseph, A. Schrott, J. Li, and C. Lam, "The impact of melting during reset operation on the reliability of phase change memory," in IEEE International Reliability Physics Symposium, Anaheim, April 2012, pp. 6C.2.1-6C.2.6.
[42] T. Y. Yang, I. M. Park, B. J. Kim, and Y. C. Joo, “Atomic migration in molten and crystalline Ge2Sb2Te5 under high electric field”, Applied Physics Letters, vol. 95, pg. 032104, June 2009.
[43] M. H. Lee, R. Cheek, C. F. Chen, Y. Zhu, J. Bruley, F. H. Baumann, Y. H. Shih, E. K. Lai, M. Breitwisch, A. Schrott, S. Raoux, E. Joseph, H. Y. Cheng, J. Y. Wu, H. L. Lung, and C. Lam, "The impact of hole-induced electromigration on the cycling endurance of phase change memory," in IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 2010, pp. 28.6.1-28.6.4.
[44] A. Padilla, G. W. Burr, K. Virwani, A. Debunne, C. T. Rettner, T. Topuria, P. M. Rice, B. Jackson, D. Dupouy, A. Kellock, R. M. Shelby, K. Gopalakrishnan, R. Shenoy, and B. Kurdi, "Voltage polarity effects in GST-based phase change memory: Physical origins and implications," in IEEE International Electron Devices Meeting, San Francisco, CA, 2010, pp. 29.4.1-29.4.4.
[45] G. Novielli, A. Ghetti, E. Varesi, A. Mauri and R. Sacco, "Atomic migration in phase change materials," in IEEE International Electron Devices Meeting, Washington, DC, 2013, pp. 22.3.1-22.3.4.
[46] R. Pearson, “Absolute Electronegativity and Hardness: Application to Inorganic Chemistry,” in Inorganic Chemistry, 1988, vol. 27, no. 4, pp 734-740.
[47] A. Redaelli, A. Pirovano, I. Tortorelli, F. Ottogalli, A. Ghetti, L. Laurin, and A. Benvenuti., "Impact of the current density increase on reliability in scaled BJT-selected PCM for high-density applications," in IEEE International Reliability Physics Symposium, Anaheim, CA, 2010, pp. 615-619.
[48] M. Boniardi, A. Redaelli, A. Ghetti and A. L. Lacaita, "Study of Cycling-Induced Parameter Variations in Phase Change Memory Cells," IEEE Electron Device Letters, vol. 34, no. 7, pp. 882-884, July 2013.
[49] S. Kim, N. Sosa, M. BrightSky, D. Mori, W. Kim, Y. Zhu, K. Suu, and C. Lam, “A phase change memory cell with metallic surfactant layer as a resistance drift stabilizer,” in IEEE International Electron Devices Meeting, Dec. 2013, pp. 30.7.1-30.7.4.
[50] W. C. Chien, Y. H. Ho, H. Y. Cheng, M. BrightSky, C. J. Chen, C. W. Yeh, T. S. Chen, W. Kim, S. Kim, J. Y. Wu, A. Ray, R. Bruce, Y. Zhu, H. Y. Ho, H. L. Lung, and C. Lam, “A novel self-converging write scheme for 2-bits/cell phase change memory for storage class memory (SCM) application,” in IEEE Symposium on VLSI Technology, 2015, pp. T100-T101.
[51] EZ-USB FX2LPTM [Online]. Received http://www.cypress.com/products/ez-usb-fx2lp.
[52] CYCLONE IV FPGAS [Online]. Received https://www.altera.com/products/fpga/cyclone-series/cyclone-iv/overview.html.
[53] A. Pirovano, A. Lacaita, F. Pellizzer, S. Kostylev, A. Benvenuti, and R. Bez, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Transaction on Electron Devices, vol. 51, no. 5, pp. 714-719, May 2004.
[54] R. Fallica, J. Battaglia, S. Cocco, C. Monguzzi, A. Teren, C. Wiemer, E. Varesi, R. Cecchini, A. Gotti, and M. Fanciulli, “Thermal and Electrical Characterization of Materials for Phase-Change Memory Cells,” Journal of Chemical and Engineering Data, vol. 54, no. 6, pp. 1698-1701, April 2009.
[55] C. Kim, D. Kang, T. Y. Lee, K. H. P. Kim, Y. S. Kang, J. Lee, S. W. Nam, K. B. Kim, and Y. Khang, “Direct evidence of phase separation in Ge2Sb2Te5 in phase change memory devices,” Applied Physics Letters, vol. 94, no. 19, pg. 193504, May 2009.
[56] N. Ciocchini, E. Palumbo, M. Borghi, P. Zuliani, R. Annunziata, and D. Ielmini, “Modeling resistance instabilities of set and reset states in phase change memory with Ge-rich GeSbTe,” IEEE Transaction on Electron Devices, vol. 61, no. 6, pp. 2136-2144, June 2014.
[57] Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data retention in MLC NAND flash memory: Characterization, optimization, and recovery,” in IEEE International Symposium on High Performance Computer Architecture, 2015, pp. 551-563.
[58] J. Y. Wu, M. Breitwisch, S. Kim, T. H. Hsu, R. Cheek, P. Y. Du, J. Li, E. K. Lai, Y. Zhu, T. Y. Wang, A. Schrott, E. Joseph, R. Dasaka, S. Raoux, M. H. Lee, H. L. Lung, and C. Lam, "A low power phase change memory using thermally confined TaN/TiN bottom electrode," in International Electron Devices Meeting, Washington, DC, Dec. 2011, pp. 3.2.1-3.2.4.
[59] IPC/JEDEC J-STD-020D [Online]. pp. 4-8, 2008.
[60] D. Ielmini, A. L. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, “Analysis of phase distribution in phase-change nonvolatile memories,” in IEEE Electron Device Letters, vol. 25, no. 7, pp. 507-509, July 2004.
[61] A. Itri, D. Ielmini, A. L. Lacaitat, A. Pirovano, E. Pellizzer, and R. Bez, “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phae-change memories,” in IEEE International Reliability Physics Symposium, pp. 209-215, April 2004.
[62] D. Ielmini, D. Mantegazza, A. L. Lacaita, A. Pirovano, and F. Pellizzer, “Parasitic reset in the programming transient of PCMs,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 799-801, Nov. 2005.
[63] D. Mantegazza, D. Ielmini, A. Priovano, and A. L. Lacaita, “Incomplete filament crystallization during set operation in PCM cells,” IEEE Electron Device Letters, vol. 31, no. 4, pp. 341-343, Apr. 2010.
[64] P. J. Nair, C. Chou, B. Rajendran, and M. K. Qureshi, “Reducing read latency of phase change memory via early read and turbo read,” in IEEE International Symposium High Performance Computer Architecture, Burlingame, CA, USA, Feb. 2015, pp. 309-319.
[65] R. A. Bheda, J. A. Poovey, J. G. Beu, and T. M. Conte, “Energy efficient Phase Change Memory based main memory for future high performance systems,” in International Green Computing Conference, Orlando, FL, USA, Jul. 2011, pp. 1-8.
[66] H. Y. Cheng, J. Y. Wu, R. Cheek, S. Raoux, M. BrightSky, D. Garbin, S. Kim, T. H. Hsu, Y. Zhu, E. K. Lai, E. Joseph, A. Schrott, S. C. Lai, A. Ray, H. L. Lung, and C. Lam, “A thermally robust phase change memory by engineering the Ge/N concentration in (Ge,N)xSbyTez phase change material,” in IEEE International Electron Devices Meeting, Dec. 2012, pp. 31.1.1-31.1.4.
[67] K. Do, D. Lee, D.-H. Ko, H. Sohn, and M.-H. Cho, “TEM Study on Volume Changes and Void Formation in Ge2Sb2Te5 Films, with Repeated Phase Changes”, Electrochemical Solid-State Letters, volume 13, issue 8, June 2010.
[68] T.-Y. Yang, J.-Y. Cho, Y.-J. Park, Y.-C. Joo, “Influence of dopants on atomic migration and void formation in molten GeSbTe under high-amplitude electrical pulse”, Acta Materialia, Volume 60, Issue 5, March 2012.