由於系統晶片複雜度、密度，以及使用的操作頻率，隨著半導體科技的進步，日益增高，導致在晶片設計中，考慮功率消耗成為非常重要的問題，例如在晶片運作的過程中，突然其來的高功率消耗，會造成晶片不穩定、壽命減短等等問題。因此準確的高階功率模型對於提前估算數位電路的功率以及優化系統晶片是非常需要且重要的。就目前為止，已經有許多方法已經被提出用來提前預測功率，例如：選擇數條重要的訊號來表示電路執行的狀態，或者是基於電路結構（平行化或控制步驟）的分解功率模型。然而電路的功率消耗通常在內部的狀態與輸入之間有相當程度上的時間關係，而許多的功率模型，沒有考慮到當前電路狀態與其過去短暫的電路狀態轉變是具有相關性的。受到深度學習的啟發，本篇論文基於先進的深度學習技術（長短期記憶的類神經網路－Long-Short Tern Memory Recurrent Neural Network），提供一個建立功率模型的方法，來更準確預測電路的每個時脈週期的功率。長短期記憶的類神經網路具有可以自主學習電路功率與電路序列（即每個時脈週期的訊號值）之間的關聯性，從實驗結果可以得知，我們所使用的長短期記憶的類神經網路，與傳統gate-level的功率模擬相比較之下，在最差的結果中，平均的功率，其百分比誤差<1.65%，而平均週期的功率百分誤差<3.74%。

Accurate high-level power modeling for digital circuits is critical to early power evaluation and
optimization for system-on-chip. Several approaches have been proposed to select critical signals
(which represent operation states) or decompose model based on circuit structures (pipelines or
control steps). However, most models ignore to take into account history of state transitions.
Inspired by deep learning, this paper presents a power modeling methodology based on long shortterm
memory (LSTM) recurrent neural network (RNN). In end-to-end learning free of hand-crafted
heuristics, RNN models can automatically capture the temporal correlation between power and a
sequence of signal values. Experimental results show that our LSTM RNN model can estimate
average power dissipation with < 1.65% errors and cycle-by-cycle power with < 3.74% errors in
the worst case, compared with gate-level power simulation.

1 Introduction 6
2 Background 10
2.0.1 A neuron - the mathematical model . . . . . . . . . . . . . . . . . . . . . 10
2.0.2 Feedforward neural networks . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0.3 Training a network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.0.3.1 Loss function . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0.3.2 Gradient descent . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0.4 Network with memory: recurrent neural network . . . . . . . . . . . . . . 15
2.0.5 LSTM networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Proposed Methodology 19
3.0.6 The proposed idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.0.7 The architecture of our network model . . . . . . . . . . . . . . . . . . . . 21
3.0.7.1 LSTM layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.0.7.2 Number of LSTM cell . . . . . . . . . . . . . . . . . . . . . . . 21
3.0.7.3 Dense layer and hidden unit . . . . . . . . . . . . . . . . . . . . 23
3.0.7.4 Linear layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.0.7.5 Loss function . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.0.7.6 Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Power Model Construction 24
4.1 Benchmark Circuit Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 ASIC flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.1 Design training set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.2 Signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.3 Input data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.4 Neural network parameter selection . . . . . . . . . . . . . . . . . . . . . 27
4.3.5 Neural network construction . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.6 Training neural network . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.7 Validation-based early stopping . . . . . . . . . . . . . . . . . . . . . . . 27
5 Experimental Result 29
5.1 Performance evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Information of experiment benchmark circuits . . . . . . . . . . . . . . . . . . . . 31
5.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Conclusions and Future Work 37

[1] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: a framework for architectural-level power
analysis and optimizations”, in Proceedings of 27th International Symposium on Computer
Architecture (IEEE Cat. No.RS00201), June 2000, pp. 83–94.
[2] A. B. Kahng, B. Lin, and S. Nath, “Orion3.0: A comprehensive noc router estimation tool”,
IEEE Embedded Systems Letters, vol. 7, no. 2, pp. 41–45, June 2015.
[3] Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, and Norman P. Jouppi, “Cacti-p:
Architecture-level modeling for sram-based structures with advanced leakage reduction techniques”,
in Proceedings of the International Conference on Computer-Aided Design, Piscataway,
NJ, USA, 2011, ICCAD ’11, pp. 694–701, IEEE Press.
[4] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “Mcpat: An
integrated power, area, and timing modeling framework for multicore and manycore architectures”,
in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO), Dec 2009, pp. 469–480.
[5] Alessandro Bogliolo, Luca Benini, and Giovanni De Micheli, “Regression-based rtl power
modeling”, ACM Trans. Des. Autom. Electron. Syst., vol. 5, no. 3, pp. 337–372, July 2000.
[6] C. W. Hsu, J. L. Liao, S. C. Fang, C. C. Weng, S. Y. Huang, W. T. Hsieh, and J. C. Yeh,
“Powerdepot: Integrating ip-based power modeling with esl power analysis for multi-core
soc designs”, in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), June
2011, pp. 47–52.
[7] S. Sch¨urmans, Diandian Zhang, D. Auras, R. Leupers, G. Ascheid, Xiaotao Chen, and Lun
Wang, “Creation of esl power models for communication architectures using automatic calibration”, in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), May 2013,
pp. 1–6.
[8] Stefan Sch¨urmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, and Xiaotao Chen, “Improving
esl power models using switching activity information from timed functional models”,
in Proceedings of the 17th International Workshop on Software and Compilers for Embedded
Systems, New York, NY, USA, 2014, SCOPES ’14, pp. 89–97, ACM.
[9] B. A. Bjrnseth, A. Djupdal, and L. Natvig, “A systematic approach to automated construction
of power emulation models”, in 2016 Design, Automation Test in Europe Conference
Exhibition (DATE), March 2016, pp. 600–605.
[10] D. Sunwoo, G. Y. Wu, N. A. Patil, and D. Chiou, “Presto: An fpga-accelerated power estimation
methodology for complex systems”, in 2010 International Conference on Field Programmable
Logic and Applications, Aug 2010, pp. 310–317.
[11] C. Bachmann, A. Genser, C. Steger, R. Weiss, and J. Haid, “Automated power characterization
for run-time power emulation of soc designs”, in 2010 13th Euromicro Conference on
Digital System Design: Architectures, Methods and Tools, Sept 2010, pp. 587–594.
[12] Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, and Tin-Fook Ngai, “Early stage real-time
soc power estimation using rtl instrumentation”, in The 20th Asia and South Pacific Design
Automation Conference, Jan 2015, pp. 779–784.
[13] K. Roy, “Neural network based macromodels for high level power estimation”, in International
Conference on Computational Intelligence and Multimedia Applications (ICCIMA
2007), Dec 2007, vol. 2, pp. 159–163.
[14] Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, and Jing-Yang Jou, “A tableless
approach for high-level power modeling using neural networks”, 2007.
[15] Wen-Tsan Hsieh, Chih-Chieh Shiue, and C. N. J. Liu, “A novel approach for high-level power
modeling of sequential circuits using recurrent neural networks”, in 2005 IEEE International
Symposium on Circuits and Systems, May 2005, pp. 3591–3594 Vol. 4.