過去四十年的技術進步是巨大的。這是由更便宜，更複雜和功能更豐富的“智能設備”。集成電路製造和應用的研究創新，發明和成長引領了這一代技術的發展。人工智能，量子計算機和物聯網承諾將推動工業革命，半導體器件將成為這三個關鍵電子新型研究領域的中堅力量。 CMOS縮放和摩爾定律是全球半導體行業的驅動力。 CMOS縮放為集成電路（IC）的每個晶體管提供（1）高性能，（2）低功率和（3）低成本。但是，隨著我們繼續大幅度縮減，統治半導體行業的Si晶體管可能無法繼續擴大規模。為了彌補這些挑戰，材料科學家的研究人員正在探索CMOS器件溝道材料以及許多新器件架構和新器件幾何結構。新材料的工藝創新和可靠性也得到了廣泛的研究。隨著我們從傳統矽器件轉向量子器件的未來，半導體器件的傳統定律不足以預測器件特性。在量子原子尺度上，亞10納米CMOSv器件中，量子限制效應不容忽視。在實際製造器件之前，由於縮放而產生的量子效應的詳細建模和仿真研究成為必須。 基於密度泛函理論（DFT），局部密度近似（LDA），廣義梯度近似（GGA），元GGA，漂移擴散，量子校正密度梯度模型，非平衡綠色函數形式化，多頻帶蒙特卡羅模擬進行了盡可能準確地預測器件特性。納米級MOSFET器件的可靠性和老化是半導體行業面臨的主要挑戰之一。當特徵尺寸被縮小時，一些必須緩解的挑戰是隨機離散摻雜劑RDD，RDD波動RDDF，多晶矽柵粒度PSG，金屬晶粒粒度MGG，隨機電信噪聲RTN，偏置溫度不穩定性BTI，陷阱輔助隧穿TAT ，界面陷阱電荷（ITC），熱預算，短溝道效應（SCE）等。使用均勻摻雜的“無接面”晶體管操作模式等新概念在10nm以下器件技術節點中具有廣闊的前景。已經提出並廣泛地研究了在溝道和源極/漏極（S / D）中包含嚴重，均勻且均勻摻雜物質的大塊和無結（JL）場效應晶體管（FET）的概念。這種JLFET器件也用適合於單片三維（3D）垂直堆疊集成電路（IC）的多晶矽薄膜晶體管（TFT）進行演示，並且繼續適用摩爾定律。而且，與JL SOI FinFET相比，通過調節襯底摻雜濃度，JL體FinFET表現出更好的短溝道特性和閾值電壓（Vth）控制。然而，JL體FinFET在製造結隔離的JL器件方面存在困難，所述JL器件不需要洩漏引起的襯底電流。另外，JL頻道必須足夠小才能實現出色的關閉特性
小維度通道使得過程控制變得困難並且可能導致增加
六
S / D中的串聯電阻隨著散裝和SOI JL FET的漏極電流的減小而變化。
我們探索超越傳統縮放路徑的器件縮放選項。本論文共分為五個部分：（1）尺度極限的矽鰭場效應晶體管（FinFET）;（2）尺度極限的鍺場效應晶體管（FinFET）;（3）矽納米線（4）研究具有不同晶體取向的鍺納米線（NW）柵極四周（GAA）晶體管。 （5）具有矽的垂直堆疊式納米薄膜柵極全能晶體管，可以擴展到FinFET之外。

Technology advancements in the last four decades is enormous. This is enabled by cheaper, more complex and functionality richer "smart devices". Research innovation, invention and growth in integrated circuit fabrication and application has lead this generation technological growth. Artificial Intelligence, Quantum computers and Internet of Things promise to take industrial revolution forward and semiconductor devices will be the backbone of these three key electronics novel research fields. CMOS scaling and Moore's law are the driving force of semiconductor industries around the globe. The CMOS scaling delivers (1) high performance, (2) low power and (3) low cost per transistor for integrated circuit (IC). But as we keep scaling down aggressively, Si transistors which ruled the semiconductor industry may not sustain the scaling anymore. To compensate the challenges, CMOS device channel materials and many new device architectures and new device geometries are being explored by researchers, material scientists. Process innovation and reliability of the new materials were also extensively researched. As we move on from conventional silicon devices to the future of quantum devices, traditional laws of semiconductor devices are not anymore enough to predict the device characteristics. At quantum atomic scales, sub 10-nm CMOS
v
devices, quantum confinement effects cannot be ignored. Detailed modeling and simulation study on quantum effects that arise due to the scaling becomes a must before actual fabrication of devices. many different simulation tools based on Density functional theory (DFT), local-density approximation (LDA), generalized gradient approximations (GGA), meta-GGA, drift diffusion, density gradient models with quantum correction, non-equilibrium green function formalism, multi-band Monte Carlo simulations were carried out to predict device characteristics as accurately as possible. Device reliability and aging in nano-scale MOSFETs is one of the main challenges within the semiconductor industry. Some of the challenges that must be alleviated when feature size is being scaled down, are random discrete Dopant RDD, RDD fluctuation RDDF, polysilicon gate granularity PSG, metal grain granularity MGG, random telegraphic noise RTN, bias temperature instabilities BTI, trap assisted tunneling TAT, interface trapped charges ITC, thermal budgets, short channel effect (SCE) etc.. New concepts like "Junctionless" transistor operation mode where homogenous doping is used has a promising future in sub 10nm device technology nodes. the concept of the bulk and junctionless (JL) field-effect-transistor (FET), which contains a heavily, uniformly, and homogeneously doping species in the channel and source/drain (S/D), has been proposed and researched extensively now. Such a JLFET device is also demonstrated with poly-Si thin film transistor (TFT), which is suitable for monolithic three dimensional (3D) vertically stacked integrated circuits (ICs) and to continue the applicability of Moore’s law. Moreover, compared with JL SOI FinFETs, JL bulk FinFETs show better short channel characteristics and threshold voltage (Vth) control by tuning substrate doping concentration. However, JL bulk FinFETs have difficulties in fabrication of the junction-isolated JL device, which needs to be free from leakage-induced substrate current. In addition, JL channel must be small enough to achieve outstanding turn-off characteristics. The small-dimensional channel makes process control difficult and possibly leads to an increase
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of the series resistance in the S/D accompanying a decrease of drain current in bulk and SOI JL FETs.
We explore options for device scaling beyond the conventional scaling path. This thesis is divided into five parts to investigate (1) Silicon Fin Field effect transistors (FinFET) at the scaling limit, (2) Germanium Fin Field effect transistors (FinFET) at the scaling limit, (3) Silicon nanowire (NW) Gate all around (GAA) transistors with atomically thin channel (4) studying Germanium nanowire (NW) Gate all around (GAA) transistors with different crystallographic orientations. (5) Vertically Stacked nanosheet gate-all-around transistors with Silicon to enable scaling beyond FinFET.
In the first part, we study silicon FinFET at scaling limit. We examine the performance of the optimized 3-nm FinFET with homogeneous source and drain doping concentration in all three modes (IM, AC & JL) of operation. The transfer and output characteristics of Inversion mode, Accumulation mode and Junctionless mode devices are discussed in detail. In addition, for each case, we interpret the 3-D electron density mesh plots. The main purpose of this paper is to provide a logical understanding of the transport properties through the simulated results as the device dimension approaches gate length (LG) of 3nm.
In the second part, we study Germanium FinFET at scaling limit. In this work, we analyzed the performance of scaled Germanium FinFETs and compared their device characteristics with a 3-nm bulk Silicon FinFET with similar device dimensions [13]. As Germanium is a potential material, this paper tries to explore the transport properties and the effect of quantum confinement on performance of Ge-based transistors. In this work, we for the first time report the charge distribution in different sub-bands of Ge devices. We have compared Si and Ge device density of states and band structure too. Junctionless (JL) devices with homogenous source drain doping will be the preferred mode of operation in ultra-scaled logic devices due to the various advantages such as reduced scattering and
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simpler device fabrication processes . Thus we comprehensively analyzed the JL mode of operation which will serve as a benchmark for future scaled device dimensions.
In the third part, we study the Silicon gate-all-around GAA transistor with atomically thin channel. A novel, high performance low-power consumption Silicon junctionless (JL) trench gate-all-around (GAA) nanowire (NWFET) transistor with atomically-thin channel for future sub-10nm technology node is demonstrated experimentally. The major problems of scaling such as, short channel effects (SCE), threshold voltage (VTH) variation, power consumption can be attenuated by using the proposed device model. The reported device with the thinnest channel shows a sub-threshold swing (SS) of 43mV/decade which has been the record to date in trench JL GAA NWFETs. Owing to the atomically-thin channel, this device has extremely high ION/IOFF current ratio of >108. Higher BTBT generation rate when channel is scaled down to <1nm leading to quantum tunneling paves a way to achieve SS value much lower than its fundamental limit. This phenomenon is confirmed with drift-diffusion (DD), density-gradient (DG) modeled 3D quantum transport TCAD device simulation.
In the fourth part, we studied the Germanium gate-all-around transistor with different crystallographic orientations. We employ a robust physics-based model solving 3D Poisson – 2D Schrödinger equation to investigate charge transport in germanium nanowire gate-all-around transistors with 3-nm gate length. We studied the effects of band structure on quantum-confined germanium and silicon nanowires. The corresponding density-of-states results were also analyzed. Different nanowire orientations have different band structure and density-of-states (DOS) due to the strong quantum-confinement effects which influence the charge carrier velocities directly. Hence, in strongly quantized germanium nanowires, change in effective masses is also significant. Analyzing the charge distribution in the different valleys and sub-bands show that multiple valley degeneracy gives high density-of-states for Ge nanowire in <110> orientation compared to <100> <111> orientations; hence, <110>
viii
oriented Ge nanowire is expected to deliver improved performance at ultra-scaled dimensions.
Finally, we modeled and simulated a stacked nanosheet gate all around GAA Silicon transistor that can enable current FinFET scaling and that had been successfully demonstrated by semiconductor leader IBM. We also analyzed the device operation in inversion and accumulation mode. Apart from the device characteristics, the circuit characteristics need to be analyzed in detailed manner. we investigated inverter operation and timing characteristics of stacked nanosheet gate all around GAA Silicon transistor operating in Junctionless mode.

Contents ..................................................................................................................................... ix
Table Captions ........................................................................................................................... xi
Figure Captions ........................................................................................................................ xii
Chapter 1 .................................................................................................................................... 1
Introduction ................................................................................................................................ 1
1-1 CMOS device Technology and evolution of Moore's law ........................................... 1
1-2 Challenges of CMOSFETs scaling .............................................................................. 5
1-3 Multi-gate structure ...................................................................................................... 5
1-4 Nano Technology based Transistors ............................................................................ 6
1-5 Junctionless Field-Effect Transistors ........................................................................... 6
A. Basic Mechanisms ................................................................................................. 7
1-6 Motivation .................................................................................................................... 9
A. Extremely Scaled Silicon Fin Field-Effect Transistor (Si FinFETs) ..................... 9
B. Extremely scaled Germanium Fin Field-Effect Transistor (Ge FinFETs)............. 9
C. Physical insights into charge transport in Germanium nanowires ....................... 10
D. Gate-All-Around Junctionless Silicon Transistors with atomically-thin nanosheet channel (0.65 nm) and Steep Subthreshold Swing (43 mV/decade) ........................ 11
1-7 Organization ............................................................................................................... 12
Chapter 2 .................................................................................................................................. 25
Extremely Scaled Silicon Fin Field-Effect Transistors ............................................................ 25
2-1 FinFET and Junctionless (JL) transistors Technology ............................................... 25
2-2 Simulation Methodology ............................................................................................ 27
A. Inversion mode (IM) .......................................................................................... 27
B. Accumulation mode (AC) .................................................................................... 27
C. Junctionless mode (JL) ........................................................................................ 28
2-3 Simulation Models ..................................................................................................... 28
2-4 Electrical Characteristics ............................................................................................ 30
2-5 3D Electron density distribution (On-state, Off-state) ............................................... 31
A. JL mode ............................................................................................................... 31
B. IM and AC mode ................................................................................................. 31
Chapter 3 .................................................................................................................................. 37
Extremely Scaled Germanium Fin Field-Effect Transistor ...................................................... 37
3-1 Introduction ................................................................................................................ 37
3-2 Device Strcuture and simulation Model ..................................................................... 38
3-3 Simulation Results and Discussion ............................................................................ 40
x
3-5 Summary of this chapter ............................................................................................ 42
Chapter 4 .................................................................................................................................. 48
Physical insights into charge transport in Germanium nanowires
4-1 Introduction ................................................................................................................ 48
4-2 Simulation method ..................................................................................................... 49
4-3 Results discussion and conclusion ............................................................................. 51
Chapter 5 .................................................................................................................................. 59
Gate-All-Around Junctionless Silicon transistors with atomically-thin Nanosheet channel (0.65 nm) and Steep Sub threshold Swing (43 mV/decade) .................................................... 59
5-1 Introduction and Device Fabrication Process ............................................................ 59
5-2 Results and Discussion ............................................................................................... 62
5-3 Conclusion .................................................................................................................. 65
Chapter 6 .................................................................................................................................. 76
Stacked Nanosheet Gate-All-Around transistor for scaling beyond FinFET ........................... 76
6-1 Stacked Nanosheet cahnnel and GAA FET in Inversion mode ................................. 76
A. Introduction ......................................................................................................... 76
6-2 Simulation Methodology ............................................................................................ 78
A. Results and Discussion ........................................................................................ 80
6-3 Conclusion.................................................................................................................82
Chapter 7 .................................................................................................................................. 88
Conclusion ................................................................................................................................ 88
Chapter 8 .................................................................................................................................. 90
Future Works Based On This Thesis ........................................................................................ 90
Reference .................................................................................................................................. 91
簡歷 Resume ......................................................................................................................... 118
著作目錄(Publication list) .................................................................................................... 122

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