這份論文研究低密度奇偶檢查碼編碼多天線系統之迭代式接收器。
首先，迭代式接收器運算複雜度高和高耗能，在實際系統中很少採用迭代式接收器。本論文提出了一種用於高吞吐量，面積效率高的迭代式接收器設計。設計面積高效的最小均方誤差平行式干擾消除檢測器已減少反矩陣運算，設計檢測器與解碼器的軟式訊息交換的介面。在考量吞吐量需求，解碼器內部迭代與外部迭代次數在吞吐量與錯誤率性能取得最好的平衡。
第二，在超密集蜂窩系統中，用戶在細胞邊緣容易受到區間干擾的影響
為了克服區間干擾的影響，本論文研究兩種迭代式區間干擾消除方法。第一種方法採用信號和干擾檢測器，使用兩個單獨檢測器消除干擾訊號。另一種方式為聯合檢測器，與兩個單獨檢測器相比，只需一半的運算複雜度，因此本論文實現聯合檢測器迭代式區間干擾消除。藉由數位座標旋轉器的處理陣列、比例增減方案和有效的對數似然比運算器可提升硬體效能。提出的迭代式區間干擾消除接收器可支援至256-QAM調變。
第三，稀疏編碼多重存取系統是一種很好的非正交多工存取技術，來解決用戶需求。但稀疏編碼多重存取系統檢測器的計算複雜度非常高，在現今文獻尚無有效的硬體架構設計。本論文提出結合最小均方誤差平行式干擾消除檢測器和訊息傳遞的演算法，並提出一個高吞吐量和低複雜度的設計，提出的檢測器支援QPSK 4x6和8x12的稀疏編碼多重存取系統並與低密度奇偶檢查碼解碼器整合為迭代式接收器。與直接對映設計相比，提出的可重組架構的低密度奇偶檢查碼解碼器與記憶體存取可減少57.1％複雜度。

This dissertation describes a study of iterative receivers for LDPC-coded MIMO systems.
First, an IDD receiver is seldom adopted in a practical system due to its high hardware complexity and accompanying power and area costs. This dissertation presents a high-throughput, area-efficient and energy-efficient IDD receiver for LDPC-coded MIMO systems. An area-efficient minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is devised to simplify matrix inversion. A detector-decoder interface that is used to exchange soft messages efficiently is proposed. Given the throughput specifications, inner and outer loops are optimally combined to maximize the error performance.
Second, users at the cell-edge are susceptible to inter-cell interference (ICI) because of the overlap of the spectrum in an ultra-dense cellular system. To combat ICI, this paper investigates two iterative ICI cancellation approaches for LDPC coded MIMO systems. One approach includes separate signal and interference detectors; the other one employs a joint detector for both the desired signal and interference. The joint-detector approach achieves a comparable error-rate performance with only half the computational complexity when compared to the separate-detector counterpart. An iterative ICI cancellation receiver using the joint detector is proposed and implemented. Its hardware efficiency is significantly enhanced by leveraging an efficient coordinate rotation digital computer (CORDIC)-based processing array, an adaptive input-range scaling scheme, and an area-efficient loglikelihood ratio (LLR) calculator. The iterative ICI cancellation receiver is flexible enough to support multiple modulations of up to 256-QAM.
Third, sparse code multiple access (SCMA) is a promising non-orthogonal multiple access (NOMA) technology to address the growing demand for massive user access. However, the computational complexity of SCMA detection is very high and efficient hardware mapping is still unavailable in the open literature. This paper presents a high-throughput, low-complexity SCMA detector that integrates the MMSE-PIC algorithm and the message-passing algorithm (MPA). It supports QPSK SCMA systems with 4 and 8 frequency bands with 6 and 12 users, respectively. The proposed SCMA detector is integrated into a LDPC-coded IDD receiver.
The interface between the SCMA detector and the LDPC decoder is designed to achieve 100% hardware utilization. The proposed reconfigurable LDPC decoder with the dedicated memory access scheme has 57.1% less hardware complexity than the direct-mapped design.

Contents
1 Introduction 1
2 Preliminary 7
2.1 LDPC Coded MIMO Systems . . . . . . . . . . . . . . . . . . . 7
2.1.1 Iterative detection and decoding . . . . . . . . . . . . . . 8
2.1.2 MIMO detector . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3 MMSE-PIC detection . . . . . . . . . . . . . . . . . . . . 13
2.1.4 LDPC decoding . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 IDD performance . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Implementation challenges . . . . . . . . . . . . . . . . . . . . . 21
3 Iterative decoding and detection receiver 23
3.1 Area-ecient of MMSE-PIC detector . . . . . . . . . . . . . . . 23
3.1.1 Division-Free MMSE-PIC Filter and LLR calculator . . 24
3.1.2 Hardware Complexity Reduction . . . . . . . . . . . . . 27
3.2 Architecture of LDPC decoder . . . . . . . . . . . . . . . . . . . 30
3.3 System integration . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 Iterative inter-cell interference cancellation receiver 40
4.1 Conventional ICI cancellation receivers for LDPC-coded MIMO
systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.1 System model . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2 Conventional ICI cancellation receivers . . . . . . . . . . 44
4.2 Iterative ICI cancellation Receiver . . . . . . . . . . . . . . . . . 45
4.2.1 Iterative ICI cancellation using separate signal and interference
detectors . . . . . . . . . . . . . . . . . . . . . 47
4.2.2 Iterative ICI cancellation using a joint signal-and-interference
detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.3 Performance evaluation . . . . . . . . . . . . . . . . . . . 53
4.3 VLSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.1 Low-complexity Joint Detector . . . . . . . . . . . . . . 58
4.3.2 Optimized interface between detector and decoder . . . . 66
4.4 Experimental Verication . . . . . . . . . . . . . . . . . . . . . 71
4.4.1 Hardware Implementation . . . . . . . . . . . . . . . . . 71
4.4.2 Performance Comparison . . . . . . . . . . . . . . . . . 73
4.5 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Iterative receiver for multiple users systems 75
5.1 LDPC-coded SCMA systems . . . . . . . . . . . . . . . . . . . . 78
5.1.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.2 MAP-based MPA Detection . . . . . . . . . . . . . . . . 81
5.1.3 LDPC Decoding . . . . . . . . . . . . . . . . . . . . . . 84
5.1.4 Iterative Detection and Decoding . . . . . . . . . . . . . 85
5.2 MMSE-Based SCMA Detection . . . . . . . . . . . . . . . . . . 86
5.2.1 Global MMSE-PIC Detection . . . . . . . . . . . . . . . 87
5.2.2 MMSE-PIC-based MPA Detection . . . . . . . . . . . . 88
5.2.3 Performance for LDPC-coded SCMA receiver . . . . . . 90
5.3 Proposed LDPC-coded SCMA Receiver with IDD . . . . . . . . 96
5.3.1 System Architecture . . . . . . . . . . . . . . . . . . . . 96
5.3.2 Multi-mode SCMA Detector . . . . . . . . . . . . . . . . 97
5.3.3 Multi-mode Multi-user LDPC Decoder Architecture . . . 103
5.3.4 Detector-Decoder Interface for IDD Processing . . . . . . 105
5.4 Performance evaluation . . . . . . . . . . . . . . . . . . . . . . . 107
5.5 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6 Conclusion 116
Appendix A 118

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