在本研究當中，利用成長在矽基板上的氮化鋁鎵/氮化鎵晶圓，製作出各種不同結構的電晶體，並利用三種不同的脈衝量測方式分析各元件潛在的不穩定性。蕭基閘極的高電子遷移率電晶體呈現穩定的閘極特性；使用P 型氮化鎵閘極的元件則會發生電洞儲存在閘極區域的P 型氮化鎵層當中，產生浮閘的效果並降低臨界電壓，本研究率先指出，閘極金屬與P 型氮化鎵層應形成良好的歐姆接觸特性，藉此消除浮閘特性並提高元件穩定性，在經過高溫熱退火後，的確有效降低臨界電壓的偏移量，由原先的-0.99 V 降低至-0.23 V；使用金氧半閘極結構的元件則呈現明顯的不穩定性，特定偏壓條件下電子會注入並束縛在氧化層內，造成臨界電壓產生約2.5 V 的改變。
除了閘極以外，磊晶層也會因產生束縛電子並影響到元件特性，此特性在所有經過測試的元件當中都有被觀察到，因為磊晶層中的束縛電子遍佈在整個元件區域下方，首先二維電子氣會因此被部分空乏，造成所有元件的導通電組上升，並影響高電子遷移率電晶體的臨界電壓，蕭基閘極電晶體的臨界電壓偏移量可達+1.5 V，而蝕刻式金氧半閘極電晶體因為同時受到介電層以及磊晶層的影響，其偏移量甚至可達到+5.7 V；對蕭基二極體而言，導通的臨界電壓不會因此改變，因為蕭基位能壘並未被束縛電子所影響；對於電晶體而言，因為閘極下方的能帶被束縛電子影響，臨界電壓因此提升。此一效應可以藉由將基板維持在浮動電位或者是接地來改善，但同時也意味了對於背面高電位型垂直元件的限制，為了驗證此特性，故利用垂直跨接結構製作了垂直型的蕭基二極體以及電晶體，磊晶層中的束縛電子的確對於高壓切換特性產生了不良影響。

In this study, the observations of instability in different AlGaN/GaN on silicon devices using three stress and pulse conditions are reported. For the schottky gate HEMT, the device characteristics are relatively stable when using pulse gate measurement, thanks to the simple gate structure, which shows nearly no trapping center under the gate region. For the p-GaN gate HEMT, if the gate metal and the p-GaN layer shows non-ohmic contact behavior, the holes are inject into the p-GaN layer in the gate region from the gate metal then stored, due to the energy well between the AlGaN layer and the barrier height from the non-ohmic contact. The importance of the property between the gate metal and the p-GaN layer to be ohmic to eliminate the storage effect and to improve the reliability was pointed out for the first time. After an anneal to improve the ohmic contact to the p-GaN gate, the threshold voltage shift was reduced from -0.99 V to -0.23 V. The MIS gate HEMT shows clearly unstable characteristics. Electrons are injected into the gate oxide then trapped from 2DEG or the gate metal, depends on the stress conditions. The trapped electrons increase the threshold voltage and show a trapping energy of 0.33 eV. The threshold voltage shift can be as large as +2.5 V for the recessed MIS gate HEMT. Another possible electron trapping location is in the epilayer, which is observed in every AlGaN/GaN on silicon devices, including TLM, SBD, and the transistors. The trapped electrons in the epilayer decrease the 2DEG density and increase the device resistance. However, those trapped electrons in the epilayer show nearly no effect on the turn-on voltage of SBDs. Because the electrons are trapped in the epilayer, which is beneath 2DEG, the schottky barrier height remains unchanged. For the transistors, the trapped electrons bend the energy
diagram under the gate region and increase the threshold voltage. A threshold voltage shift of +1.5 V was observed in Schottky gate HEMT. The recessed MIS gate HEMT shows a +5.7 V threshold voltage shift due to the electrons trapped in the epilayer and the gate dielectric. The extracted trapping energy in the epilayer is about 0.5 eV in this study. This effect can be minimized by grounding or floating the silicon substrate, which might limits the applications of vertical devices with a rear high voltage electrode. A vertical SBD and a vertical schottky gate HEMT with a vertical interconnect structure, are fabricated for confirmation. For the vertical cathode SBD and the vertical drain schottky gate HEMT, a great increment of on-resistance is observed using pulse measurement compared with other devices with different interconnect structures.

Chapter 1 Introduction ................................................................................................ 1
1.1 Material Property ....................................................................................... 1
1.2 Epilayer Structure and Growth .................................................................. 6
1.3 Device Structure......................................................................................... 9
1.4 Motivation ................................................................................................ 12
Chapter 2 Fabrication and Process Flow .................................................................. 14
2.1 Introduction .............................................................................................. 14
2.2 Epi structures ........................................................................................... 15
2.3 Process Flow for a Schottky Gate HEMT ................................................ 16
2.3.1 Sample Preparation ...................................................................... 16
2.3.2 Alignment Key and Ohmic Metal ................................................ 17
2.3.3 Isolation........................................................................................ 17
2.3.4 Passivation Layer and Field Oxide .............................................. 18
2.3.5 Contact Window ........................................................................... 19
2.3.6 Gate Metal and Pad Metal ............................................................ 19
2.4 Process Flow for a p-GaN Gate HEMT ................................................... 20
2.4.1 Sample Preparation ...................................................................... 20
2.4.2 Alignment Key and Ohmic Metal ................................................ 20
2.4.3 Isolation........................................................................................ 21
2.4.4 Gate Metal .................................................................................... 22
2.4.5 p-GaN Etching ............................................................................. 22
2.4.6 Passivation Layer and Field Oxide .............................................. 23
2.4.7 Contact Window ........................................................................... 23
2.4.8 Pad Metal ..................................................................................... 24
2.5 Process Flow for Recessed MIS Gate HEMT .......................................... 25
2.5.1 Sample Preparation ...................................................................... 25
2.5.2 Alignment Key and Body Contact Etching ................................. 26
2.5.3 Gate Recess .................................................................................. 26
2.5.4 Gate Dielectric and Passivation Layer ......................................... 27
2.5.5 Ohmic Metal ................................................................................ 28
2.5.6 Isolation........................................................................................ 28
2.5.7 Gate Metal, Pad Metal, and Body Contact Metal ........................ 28
Chapter 3 Instability from the Gate .......................................................................... 31
3.1 Introduction .............................................................................................. 31
3.2 DC Measurement or Pulse Measurement ................................................ 32
3.3 Resistor Network Model .......................................................................... 35
3.4 Gate Instability in Schottky Gate HEMT................................................. 38
3.5 Gate Instability in p-GaN Gate HEMT .................................................... 41
3.6 Gate Instability in Recessed MIS Gate HEMT ........................................ 51
3.7 Summary .................................................................................................. 57
Chapter 4 Instability from Body ............................................................................... 60
4.1 Introduction .............................................................................................. 60
4.2 Body Instability in Schottky Barrier Diode ............................................. 61
4.3 Body Instability in Schottky Gate HEMT ............................................... 63
4.4 Body Instability in Recessed MIS Gate HEMT ....................................... 65
4.5 Summary .................................................................................................. 68
Chapter 5 Instability from Substrate ......................................................................... 70
5.1 Introduction .............................................................................................. 70
5.2 The Influence of Epilayer Traps in TLM and SBD ................................. 72
5.3 The Influence of Epilayer Traps on HEMTs ............................................ 74
5.4 Summary .................................................................................................. 77
Chapter 6 Instability of AlGaN/GaN Devices on Silicon with Vertical Interconnect
Structure ................................................................................................... 81
6.1 Introduction .............................................................................................. 81
6.2 Schottky Barrier Diode with Vertical Interconnect Structure .................. 83
6.3 HEMTs with Vertical Interconnect Structure ........................................... 87
6.4 Summary .................................................................................................. 92
Chapter 7 Conclusion and Future Work ................................................................... 93
7.1 Conclusion ............................................................................................... 93
7.2 Future Work ............................................................................................. 96
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